1a80490c5SAndre Przywara# 2a80490c5SAndre Przywara# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3a80490c5SAndre Przywara# 4a80490c5SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5a80490c5SAndre Przywara# 6a80490c5SAndre Przywara 7a80490c5SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 8a80490c5SAndre Przywara 9a80490c5SAndre PrzywaraAW_PLAT := plat/allwinner 10a80490c5SAndre Przywara 11a80490c5SAndre PrzywaraPLAT_INCLUDES := -Iinclude/plat/arm/common \ 12a80490c5SAndre Przywara -Iinclude/plat/arm/common/aarch64 \ 13a80490c5SAndre Przywara -I${AW_PLAT}/common/include \ 14a80490c5SAndre Przywara -I${AW_PLAT}/${PLAT}/include 15a80490c5SAndre Przywara 16*41538930SAndre Przywarainclude lib/libfdt/libfdt.mk 17*41538930SAndre Przywara 18a80490c5SAndre PrzywaraPLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \ 19a80490c5SAndre Przywara drivers/ti/uart/${ARCH}/16550_console.S \ 20a80490c5SAndre Przywara ${XLAT_TABLES_LIB_SRCS} \ 21a80490c5SAndre Przywara ${AW_PLAT}/common/plat_helpers.S \ 22a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_common.c 23a80490c5SAndre Przywara 24a80490c5SAndre PrzywaraBL31_SOURCES += drivers/arm/gic/common/gic_common.c \ 25a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_helpers.c \ 26a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_main.c \ 27a80490c5SAndre Przywara drivers/delay_timer/delay_timer.c \ 28a80490c5SAndre Przywara drivers/delay_timer/generic_delay_timer.c \ 29a80490c5SAndre Przywara lib/cpus/${ARCH}/cortex_a53.S \ 30a80490c5SAndre Przywara plat/common/plat_gicv2.c \ 31a80490c5SAndre Przywara plat/common/plat_psci_common.c \ 32a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_bl31_setup.c \ 33a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_cpu_ops.c \ 34a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_pm.c \ 35a80490c5SAndre Przywara ${AW_PLAT}/${PLAT}/sunxi_power.c \ 36a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_security.c \ 37a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_topology.c 38a80490c5SAndre Przywara 39a80490c5SAndre Przywara# The bootloader is guaranteed to only run on CPU 0 by the boot ROM. 40a80490c5SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 1 41a80490c5SAndre Przywara 42a80490c5SAndre Przywara# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. 43a80490c5SAndre PrzywaraERRATA_A53_835769 := 1 44a80490c5SAndre PrzywaraERRATA_A53_843419 := 1 45a80490c5SAndre PrzywaraERRATA_A53_855873 := 1 46a80490c5SAndre Przywara 47a80490c5SAndre PrzywaraMULTI_CONSOLE_API := 1 48a80490c5SAndre Przywara 49a80490c5SAndre Przywara# The reset vector can be changed for each CPU. 50a80490c5SAndre PrzywaraPROGRAMMABLE_RESET_ADDRESS := 1 51a80490c5SAndre Przywara 52a80490c5SAndre Przywara# Allow mapping read-only data as execute-never. 53a80490c5SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 54a80490c5SAndre Przywara 55a80490c5SAndre Przywara# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL 56a80490c5SAndre PrzywaraRESET_TO_BL31 := 1 5743060513SAndre Przywara 5843060513SAndre Przywara# We are short on memory, so save 3.5KB by not having an extra coherent page. 5943060513SAndre PrzywaraUSE_COHERENT_MEM := 0 60