1a80490c5SAndre Przywara# 2fb23b104SSamuel Holland# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3a80490c5SAndre Przywara# 4a80490c5SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5a80490c5SAndre Przywara# 6a80490c5SAndre Przywara 7a80490c5SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 89bc28a5eSAndre Przywarainclude lib/libfdt/libfdt.mk 99bc28a5eSAndre Przywarainclude drivers/arm/gic/v2/gicv2.mk 10a80490c5SAndre Przywara 11a80490c5SAndre PrzywaraAW_PLAT := plat/allwinner 12a80490c5SAndre Przywara 13252c1d1dSSamuel HollandPLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \ 14a80490c5SAndre Przywara -I${AW_PLAT}/common/include \ 15a80490c5SAndre Przywara -I${AW_PLAT}/${PLAT}/include 16a80490c5SAndre Przywara 17985ee0b7SJulius WernerPLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ 18a80490c5SAndre Przywara ${XLAT_TABLES_LIB_SRCS} \ 19a80490c5SAndre Przywara ${AW_PLAT}/common/plat_helpers.S \ 20a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_common.c 21a80490c5SAndre Przywara 22fb23b104SSamuel HollandBL31_SOURCES += drivers/allwinner/axp/common.c \ 2350cabf6dSSamuel Holland drivers/allwinner/sunxi_msgbox.c \ 24e382c88eSSamuel Holland drivers/arm/css/scpi/css_scpi.c \ 259bc28a5eSAndre Przywara ${GICV2_SOURCES} \ 26a80490c5SAndre Przywara drivers/delay_timer/delay_timer.c \ 27a80490c5SAndre Przywara drivers/delay_timer/generic_delay_timer.c \ 28a80490c5SAndre Przywara lib/cpus/${ARCH}/cortex_a53.S \ 29a80490c5SAndre Przywara plat/common/plat_gicv2.c \ 30a80490c5SAndre Przywara plat/common/plat_psci_common.c \ 31a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_bl31_setup.c \ 32a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_cpu_ops.c \ 33a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_pm.c \ 34a80490c5SAndre Przywara ${AW_PLAT}/${PLAT}/sunxi_power.c \ 35a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_security.c \ 36a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_topology.c 37a80490c5SAndre Przywara 38a80490c5SAndre Przywara# The bootloader is guaranteed to only run on CPU 0 by the boot ROM. 39a80490c5SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 1 40a80490c5SAndre Przywara 418f31853bSSamuel Holland# Do not enable SPE (not supported on ARM v8.0). 428f31853bSSamuel HollandENABLE_SPE_FOR_LOWER_ELS := 0 438f31853bSSamuel Holland 448f31853bSSamuel Holland# Do not enable SVE (not supported on ARM v8.0). 458f31853bSSamuel HollandENABLE_SVE_FOR_NS := 0 468f31853bSSamuel Holland 47a80490c5SAndre Przywara# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. 48a80490c5SAndre PrzywaraERRATA_A53_835769 := 1 49a80490c5SAndre PrzywaraERRATA_A53_843419 := 1 50a80490c5SAndre PrzywaraERRATA_A53_855873 := 1 51a80490c5SAndre Przywara 52*3d36d8e6SSamuel Holland# The traditional U-Boot load address is 160MB into DRAM. 53*3d36d8e6SSamuel HollandPRELOADED_BL33_BASE ?= 0x4a000000 54*3d36d8e6SSamuel Holland 55a80490c5SAndre Przywara# The reset vector can be changed for each CPU. 56a80490c5SAndre PrzywaraPROGRAMMABLE_RESET_ADDRESS := 1 57a80490c5SAndre Przywara 58a80490c5SAndre Przywara# Allow mapping read-only data as execute-never. 59a80490c5SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 60a80490c5SAndre Przywara 61ed306a86SSamuel Holland# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL. 62ed306a86SSamuel HollandSEPARATE_NOBITS_REGION := 1 63ed306a86SSamuel Holland 64a80490c5SAndre Przywara# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL 65a80490c5SAndre PrzywaraRESET_TO_BL31 := 1 6643060513SAndre Przywara 678f31853bSSamuel Holland# This platform is single-cluster and does not require coherency setup. 688f31853bSSamuel HollandWARMBOOT_ENABLE_DCACHE_EARLY := 1 69