1# 2# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# By default, consider that the platform may release several CPUs out of reset. 37# The platform Makefile is free to override this value. 38COLD_BOOT_SINGLE_CPU := 0 39 40# Flag to compile in coreboot support code. Exclude by default. The coreboot 41# Makefile system will set this when compiling TF as part of a coreboot image. 42COREBOOT := 0 43 44# For Chain of Trust 45CREATE_KEYS := 1 46 47# Build flag to include AArch32 registers in cpu context save and restore during 48# world switch. This flag must be set to 0 for AArch64-only platforms. 49CTX_INCLUDE_AARCH32_REGS := 1 50 51# Include FP registers in cpu context 52CTX_INCLUDE_FPREGS := 0 53 54# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 55# must be set to 1 if the platform wants to use this feature in the Secure 56# world. It is not needed to use it in the Non-secure world. 57CTX_INCLUDE_PAUTH_REGS := 0 58 59# Debug build 60DEBUG := 0 61 62# Build platform 63DEFAULT_PLAT := fvp 64 65# Enable capability to disable authentication dynamically. Only meant for 66# development platforms. 67DYN_DISABLE_AUTH := 0 68 69# Build option to enable MPAM for lower ELs 70ENABLE_MPAM_FOR_LOWER_ELS := 0 71 72# Flag to Enable Position Independant support (PIE) 73ENABLE_PIE := 0 74 75# Flag to enable Performance Measurement Framework 76ENABLE_PMF := 0 77 78# Flag to enable PSCI STATs functionality 79ENABLE_PSCI_STAT := 0 80 81# Flag to enable runtime instrumentation using PMF 82ENABLE_RUNTIME_INSTRUMENTATION := 0 83 84# Flag to enable stack corruption protection 85ENABLE_STACK_PROTECTOR := 0 86 87# Flag to enable exception handling in EL3 88EL3_EXCEPTION_HANDLING := 0 89 90# Flag to enable Pointer Authentication 91ENABLE_PAUTH := 0 92 93# Build flag to treat usage of deprecated platform and framework APIs as error. 94ERROR_DEPRECATED := 0 95 96# Fault injection support 97FAULT_INJECTION_SUPPORT := 0 98 99# Byte alignment that each component in FIP is aligned to 100FIP_ALIGN := 0 101 102# Default FIP file name 103FIP_NAME := fip.bin 104 105# Default FWU_FIP file name 106FWU_FIP_NAME := fwu_fip.bin 107 108# For Chain of Trust 109GENERATE_COT := 0 110 111# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 112# default, they are for Secure EL1. 113GICV2_G0_FOR_EL3 := 0 114 115# Route External Aborts to EL3. Disabled by default; External Aborts are handled 116# by lower ELs. 117HANDLE_EA_EL3_FIRST := 0 118 119# Whether system coherency is managed in hardware, without explicit software 120# operations. 121HW_ASSISTED_COHERENCY := 0 122 123# Set the default algorithm for the generation of Trusted Board Boot keys 124KEY_ALG := rsa 125 126# Enable use of the console API allowing multiple consoles to be registered 127# at the same time. 128MULTI_CONSOLE_API := 0 129 130# NS timer register save and restore 131NS_TIMER_SWITCH := 0 132 133# Include lib/libc in the final image 134OVERRIDE_LIBC := 0 135 136# Build PL011 UART driver in minimal generic UART mode 137PL011_GENERIC_UART := 0 138 139# By default, consider that the platform's reset address is not programmable. 140# The platform Makefile is free to override this value. 141PROGRAMMABLE_RESET_ADDRESS := 0 142 143# Flag used to choose the power state format: Extended State-ID or Original 144PSCI_EXTENDED_STATE_ID := 0 145 146# Enable RAS support 147RAS_EXTENSION := 0 148 149# By default, BL1 acts as the reset handler, not BL31 150RESET_TO_BL31 := 0 151 152# For Chain of Trust 153SAVE_KEYS := 0 154 155# Software Delegated Exception support 156SDEI_SUPPORT := 0 157 158# Whether code and read-only data should be put on separate memory pages. The 159# platform Makefile is free to override this value. 160SEPARATE_CODE_AND_RODATA := 0 161 162# If the BL31 image initialisation code is recalimed after use for the secondary 163# cores stack 164RECLAIM_INIT_CODE := 0 165 166# SPD choice 167SPD := none 168 169# For including the Secure Partition Manager 170ENABLE_SPM := 0 171 172# Use the SPM based on MM 173SPM_MM := 1 174 175# Flag to introduce an infinite loop in BL1 just before it exits into the next 176# image. This is meant to help debugging the post-BL2 phase. 177SPIN_ON_BL1_EXIT := 0 178 179# Flags to build TF with Trusted Boot support 180TRUSTED_BOARD_BOOT := 0 181 182# Build option to choose whether Trusted Firmware uses Coherent memory or not. 183USE_COHERENT_MEM := 1 184 185# Build option to choose whether Trusted Firmware uses library at ROM 186USE_ROMLIB := 0 187 188# Use tbbr_oid.h instead of platform_oid.h 189USE_TBBR_DEFS := 1 190 191# Build verbosity 192V := 0 193 194# Whether to enable D-Cache early during warm boot. This is usually 195# applicable for platforms wherein interconnect programming is not 196# required to enable cache coherency after warm reset (eg: single cluster 197# platforms). 198WARMBOOT_ENABLE_DCACHE_EARLY := 0 199 200# Build option to enable/disable the Statistical Profiling Extensions 201ENABLE_SPE_FOR_LOWER_ELS := 1 202 203# SPE is only supported on AArch64 so disable it on AArch32. 204ifeq (${ARCH},aarch32) 205 override ENABLE_SPE_FOR_LOWER_ELS := 0 206endif 207 208ENABLE_AMU := 0 209 210# By default, enable Scalable Vector Extension if implemented for Non-secure 211# lower ELs 212# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 213ifneq (${ARCH},aarch32) 214 ENABLE_SVE_FOR_NS := 1 215else 216 override ENABLE_SVE_FOR_NS := 0 217endif 218