1# 2# Copyright (c) 2016-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include SVE registers in cpu context 67CTX_INCLUDE_SVE_REGS := 0 68 69# Debug build 70DEBUG := 0 71 72# By default disable authenticated decryption support. 73DECRYPTION_SUPPORT := none 74 75# Build platform 76DEFAULT_PLAT := fvp 77 78# Disable the generation of the binary image (ELF only). 79DISABLE_BIN_GENERATION := 0 80 81# Enable capability to disable authentication dynamically. Only meant for 82# development platforms. 83DYN_DISABLE_AUTH := 0 84 85# Enable the Maximum Power Mitigation Mechanism on supporting cores. 86ENABLE_MPMM := 0 87 88# Enable support for powerdown abandons 89FEAT_PABANDON := 0 90 91# Flag to Enable Position Independant support (PIE) 92ENABLE_PIE := 0 93 94# Flag to enable Performance Measurement Framework 95ENABLE_PMF := 0 96 97# Flag to enable PSCI STATs functionality 98ENABLE_PSCI_STAT := 0 99 100# Flag to enable runtime instrumentation using PMF 101ENABLE_RUNTIME_INSTRUMENTATION := 0 102 103# Flag to enable stack corruption protection 104ENABLE_STACK_PROTECTOR := 0 105 106# Flag to enable exception handling in EL3 107EL3_EXCEPTION_HANDLING := 0 108 109# Flag to include all errata for all CPUs TF-A implements workarounds for 110# Its supposed to be used only for testing. 111ENABLE_ERRATA_ALL := 0 112 113# By default BL31 encryption disabled 114ENCRYPT_BL31 := 0 115 116# By default BL32 encryption disabled 117ENCRYPT_BL32 := 0 118 119# Default dummy firmware encryption key 120ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 121 122# Default dummy nonce for firmware encryption 123ENC_NONCE := 1234567890abcdef12345678 124 125# Build flag to treat usage of deprecated platform and framework APIs as error. 126ERROR_DEPRECATED := 0 127 128# Fault injection support 129FAULT_INJECTION_SUPPORT := 0 130 131# Flag to enable architectural features detection mechanism 132FEATURE_DETECTION := 0 133 134# Byte alignment that each component in FIP is aligned to 135FIP_ALIGN := 0 136 137# Default FIP file name 138FIP_NAME := fip.bin 139 140# Default FWU_FIP file name 141FWU_FIP_NAME := fwu_fip.bin 142 143# By default firmware encryption with SSK 144FW_ENC_STATUS := 0 145 146# For Chain of Trust 147GENERATE_COT := 0 148 149# Default number of 512 blocks per bitlock 150RME_GPT_BITLOCK_BLOCK := 1 151 152# Default maximum size of GPT contiguous block 153RME_GPT_MAX_BLOCK := 512 154 155# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 156# default, they are for Secure EL1. 157GICV2_G0_FOR_EL3 := 0 158 159# Generic implementation of a GICvX driver 160USE_GIC_DRIVER := 0 161 162# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 163# by lower ELs. 164HANDLE_EA_EL3_FIRST_NS := 0 165 166# Enable Handoff protocol using transfer lists 167TRANSFER_LIST := 0 168 169# Enable HOB list to generate boot information 170HOB_LIST := 0 171 172# Enables support for the gcc compiler option "-mharden-sls=all". 173# By default, disables all SLS hardening. 174HARDEN_SLS := 0 175 176# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 177# The default value is sha256. 178HASH_ALG := sha256 179 180# Whether system coherency is managed in hardware, without explicit software 181# operations. 182HW_ASSISTED_COHERENCY := 0 183 184# Flag to enable trapping of implementation defined sytem registers 185IMPDEF_SYSREG_TRAP := 0 186 187# Set the default algorithm for the generation of Trusted Board Boot keys 188KEY_ALG := rsa 189 190# Set the default key size in case KEY_ALG is rsa 191ifeq ($(KEY_ALG),rsa) 192KEY_SIZE := 2048 193endif 194 195# Option to build TF with Measured Boot support 196MEASURED_BOOT := 0 197 198# Option to build TF with Discrete TPM support 199DISCRETE_TPM := 0 200 201# Option to enable the DICE Protection Environmnet as a Measured Boot backend 202DICE_PROTECTION_ENVIRONMENT :=0 203 204# NS timer register save and restore 205NS_TIMER_SWITCH := 0 206 207# Include lib/libc in the final image 208OVERRIDE_LIBC := 0 209 210# Build PL011 UART driver in minimal generic UART mode 211PL011_GENERIC_UART := 0 212 213# By default, consider that the platform's reset address is not programmable. 214# The platform Makefile is free to override this value. 215PROGRAMMABLE_RESET_ADDRESS := 0 216 217# Flag used to choose the power state format: Extended State-ID or Original 218PSCI_EXTENDED_STATE_ID := 0 219 220# Enable PSCI OS-initiated mode support 221PSCI_OS_INIT_MODE := 0 222 223# SMCCC_ARCH_FEATURE_AVAILABILITY support 224ARCH_FEATURE_AVAILABILITY := 0 225 226# By default, BL1 acts as the reset handler, not BL31 227RESET_TO_BL31 := 0 228 229# For Chain of Trust 230SAVE_KEYS := 0 231 232# Software Delegated Exception support 233SDEI_SUPPORT := 0 234 235# True Random Number firmware Interface support 236TRNG_SUPPORT := 0 237 238# Check to see if Errata ABI is supported 239ERRATA_ABI_SUPPORT := 0 240 241# Check to enable Errata ABI for platforms with non-arm interconnect 242ERRATA_NON_ARM_INTERCONNECT := 0 243 244# SMCCC PCI support 245SMC_PCI_SUPPORT := 0 246 247# Whether code and read-only data should be put on separate memory pages. The 248# platform Makefile is free to override this value. 249SEPARATE_CODE_AND_RODATA := 0 250 251# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 252# separate memory region, which may be discontiguous from the rest of BL31. 253SEPARATE_NOBITS_REGION := 0 254 255# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 256# region, platform Makefile is free to override this value. 257SEPARATE_BL2_NOLOAD_REGION := 0 258 259# Put RW DATA sections (.rwdata) in a separate memory region, which may be 260# discontiguous from the rest of BL31. 261SEPARATE_RWDATA_REGION := 0 262 263# Put SIMD context data structures in a separate memory region. Platforms 264# have the choice to put it outside of default BSS region of EL3 firmware. 265SEPARATE_SIMD_SECTION := 0 266 267# If the BL31 image initialisation code is recalimed after use for the secondary 268# cores stack 269RECLAIM_INIT_CODE := 0 270 271# SPD choice 272SPD := none 273 274# Enable the Management Mode (MM)-based Secure Partition Manager implementation 275SPM_MM := 0 276 277# Use the FF-A SPMC implementation in EL3. 278SPMC_AT_EL3 := 0 279 280# Enable SEL0 SP when SPMC is enabled at EL3 281SPMC_AT_EL3_SEL0_SP :=0 282 283# Use SPM at S-EL2 as a default config for SPMD 284SPMD_SPM_AT_SEL2 := 1 285 286# Flag to introduce an infinite loop in BL1 just before it exits into the next 287# image. This is meant to help debugging the post-BL2 phase. 288SPIN_ON_BL1_EXIT := 0 289 290# Flags to build TF with Trusted Boot support 291TRUSTED_BOARD_BOOT := 0 292 293# Build option to choose whether Trusted Firmware uses Coherent memory or not. 294USE_COHERENT_MEM := 1 295 296# Build option to add debugfs support 297USE_DEBUGFS := 0 298 299# Build option to fconf based io 300ARM_IO_IN_DTB := 0 301 302# Build option to support SDEI through fconf 303SDEI_IN_FCONF := 0 304 305# Build option to support Secure Interrupt descriptors through fconf 306SEC_INT_DESC_IN_FCONF := 0 307 308# Build option to choose whether Trusted Firmware uses library at ROM 309USE_ROMLIB := 0 310 311# Build option to choose whether the xlat tables of BL images can be read-only. 312# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 313# which is the per BL-image option that actually enables the read-only tables 314# API. The reason for having this additional option is to have a common high 315# level makefile where we can check for incompatible features/build options. 316ALLOW_RO_XLAT_TABLES := 0 317 318# Chain of trust. 319COT := tbbr 320 321# Use tbbr_oid.h instead of platform_oid.h 322USE_TBBR_DEFS := 1 323 324# Whether to enable D-Cache early during warm boot. This is usually 325# applicable for platforms wherein interconnect programming is not 326# required to enable cache coherency after warm reset (eg: single cluster 327# platforms). 328WARMBOOT_ENABLE_DCACHE_EARLY := 0 329 330# Default SVE vector length to maximum architected value 331SVE_VECTOR_LEN := 2048 332 333SANITIZE_UB := off 334 335# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 336# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 337# Default: disabled 338USE_SPINLOCK_CAS := 0 339 340# Enable Link Time Optimization 341ENABLE_LTO := 0 342 343# This option will include EL2 registers in cpu context save and restore during 344# EL2 firmware entry/exit. Internal flag not meant for direct setting. 345# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 346# CTX_INCLUDE_EL2_REGS. 347CTX_INCLUDE_EL2_REGS := 0 348 349# Select workaround for AT speculative behaviour. 350ERRATA_SPECULATIVE_AT := 0 351 352# select workaround for SME aborting powerdown 353ERRATA_SME_POWER_DOWN := 0 354 355# Trap RAS error record access from Non secure 356RAS_TRAP_NS_ERR_REC_ACCESS := 0 357 358# Build option to create cot descriptors using fconf 359COT_DESC_IN_DTB := 0 360 361# Build option to provide OpenSSL directory path 362OPENSSL_DIR := /usr 363 364# Select the openssl binary provided in OPENSSL_DIR variable 365ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 366 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 367else 368 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 369endif 370 371# Build option to use the SP804 timer instead of the generic one 372USE_SP804_TIMER := 0 373 374# Build option to define number of firmware banks, used in firmware update 375# metadata structure. 376NR_OF_FW_BANKS := 2 377 378# Build option to define number of images in firmware bank, used in firmware 379# update metadata structure. 380NR_OF_IMAGES_IN_FW_BANK := 1 381 382# Disable Firmware update support by default 383PSA_FWU_SUPPORT := 0 384 385# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 386# is enabled. 387ifeq ($(PSA_FWU_SUPPORT),1) 388PSA_FWU_METADATA_FW_STORE_DESC := 1 389else 390PSA_FWU_METADATA_FW_STORE_DESC := 0 391endif 392 393# Dynamic Root of Trust for Measurement support 394DRTM_SUPPORT := 0 395 396# Check platform if cache management operations should be performed. 397# Disabled by default. 398CONDITIONAL_CMO := 0 399 400# By default, disable SPMD Logical partitions 401ENABLE_SPMD_LP := 0 402 403# By default, disable PSA crypto (use MbedTLS legacy crypto API). 404PSA_CRYPTO := 0 405 406# getc() support from the console(s). 407# Disabled by default because it constitutes an attack vector into TF-A. It 408# should only be enabled if there is a use case for it. 409ENABLE_CONSOLE_GETC := 0 410 411# Build option to disable EL2 when it is not used. 412# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 413# functions must be enabled by platforms if they require it. 414# Disabled by default. 415INIT_UNUSED_NS_EL2 := 0 416 417# Disable including MPAM EL2 registers in context by default since currently 418# it's only enabled for NS world 419CTX_INCLUDE_MPAM_REGS := 0 420 421# Enable context memory usage reporting during BL31 setup. 422PLATFORM_REPORT_CTX_MEM_USE := 0 423 424# Enable early console 425EARLY_CONSOLE := 0 426 427# Allow platforms to save/restore DSU PMU registers over a power cycle. 428# Disabled by default and must be enabled by individual platforms. 429PRESERVE_DSU_PMU_REGS := 0 430 431# Enable RMMD to forward attestation requests from RMM to EL3. 432RMMD_ENABLE_EL3_TOKEN_SIGN := 0 433 434# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP). 435# This flag is temporary and it is expected once the interface is 436# finalized, this flag will be removed. 437RMMD_ENABLE_IDE_KEY_PROG := 0 438 439# Live firmware activation support 440LFA_SUPPORT := 0 441