1# 2# Copyright (c) 2016-2022, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when BL2_AT_EL3 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 67# must be set to 1 if the platform wants to use this feature in the Secure 68# world. It is not needed to use it in the Non-secure world. 69CTX_INCLUDE_PAUTH_REGS := 0 70 71# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 72# This must be set to 1 if architecture implements Nested Virtualization 73# Extension and platform wants to use this feature in the Secure world 74CTX_INCLUDE_NEVE_REGS := 0 75 76# Debug build 77DEBUG := 0 78 79# By default disable authenticated decryption support. 80DECRYPTION_SUPPORT := none 81 82# Build platform 83DEFAULT_PLAT := fvp 84 85# Disable the generation of the binary image (ELF only). 86DISABLE_BIN_GENERATION := 0 87 88# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 89# compatibility. 90DISABLE_MTPMU := 0 91 92# Enable capability to disable authentication dynamically. Only meant for 93# development platforms. 94DYN_DISABLE_AUTH := 0 95 96# Build option to enable MPAM for lower ELs 97ENABLE_MPAM_FOR_LOWER_ELS := 0 98 99# Enable the Maximum Power Mitigation Mechanism on supporting cores. 100ENABLE_MPMM := 0 101 102# Enable MPMM configuration via FCONF. 103ENABLE_MPMM_FCONF := 0 104 105# Flag to Enable Position Independant support (PIE) 106ENABLE_PIE := 0 107 108# Flag to enable Performance Measurement Framework 109ENABLE_PMF := 0 110 111# Flag to enable PSCI STATs functionality 112ENABLE_PSCI_STAT := 0 113 114# Flag to enable Realm Management Extension (FEAT_RME) 115ENABLE_RME := 0 116 117# Flag to enable runtime instrumentation using PMF 118ENABLE_RUNTIME_INSTRUMENTATION := 0 119 120# Flag to enable stack corruption protection 121ENABLE_STACK_PROTECTOR := 0 122 123# Flag to enable exception handling in EL3 124EL3_EXCEPTION_HANDLING := 0 125 126# Flag to enable Branch Target Identification. 127# Internal flag not meant for direct setting. 128# Use BRANCH_PROTECTION to enable BTI. 129ENABLE_BTI := 0 130 131# Flag to enable Pointer Authentication. 132# Internal flag not meant for direct setting. 133# Use BRANCH_PROTECTION to enable PAUTH. 134ENABLE_PAUTH := 0 135 136# Flag to enable access to the HAFGRTR_EL2 register 137ENABLE_FEAT_AMUv1 := 0 138 139# Flag to enable AMUv1p1 extension. 140ENABLE_FEAT_AMUv1p1 := 0 141 142# Flag to enable CSV2_2 extension. 143ENABLE_FEAT_CSV2_2 := 0 144 145# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 146ENABLE_FEAT_HCX := 0 147 148# Flag to enable access to the HDFGRTR_EL2 register 149ENABLE_FEAT_FGT := 0 150 151# Flag to enable access to the CNTPOFF_EL2 register 152ENABLE_FEAT_ECV := 0 153 154# Flag to enable use of the DIT feature. 155ENABLE_FEAT_DIT := 0 156 157# Flag to enable access to Privileged Access Never bit of PSTATE. 158ENABLE_FEAT_PAN := 0 159 160# Flag to enable access to the Random Number Generator registers 161ENABLE_FEAT_RNG := 0 162 163# Flag to enable Speculation Barrier Instruction 164ENABLE_FEAT_SB := 0 165 166# Flag to enable Secure EL-2 feature. 167ENABLE_FEAT_SEL2 := 0 168 169# Flag to enable Virtualization Host Extensions 170ENABLE_FEAT_VHE := 0 171 172# By default BL31 encryption disabled 173ENCRYPT_BL31 := 0 174 175# By default BL32 encryption disabled 176ENCRYPT_BL32 := 0 177 178# Default dummy firmware encryption key 179ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 180 181# Default dummy nonce for firmware encryption 182ENC_NONCE := 1234567890abcdef12345678 183 184# Build flag to treat usage of deprecated platform and framework APIs as error. 185ERROR_DEPRECATED := 0 186 187# Fault injection support 188FAULT_INJECTION_SUPPORT := 0 189 190# Flag to enable architectural features detection mechanism 191FEATURE_DETECTION := 0 192 193# Byte alignment that each component in FIP is aligned to 194FIP_ALIGN := 0 195 196# Default FIP file name 197FIP_NAME := fip.bin 198 199# Default FWU_FIP file name 200FWU_FIP_NAME := fwu_fip.bin 201 202# By default firmware encryption with SSK 203FW_ENC_STATUS := 0 204 205# For Chain of Trust 206GENERATE_COT := 0 207 208# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 209# default, they are for Secure EL1. 210GICV2_G0_FOR_EL3 := 0 211 212# Route External Aborts to EL3. Disabled by default; External Aborts are handled 213# by lower ELs. 214HANDLE_EA_EL3_FIRST := 0 215 216# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 217# The default value is sha256. 218HASH_ALG := sha256 219 220# Whether system coherency is managed in hardware, without explicit software 221# operations. 222HW_ASSISTED_COHERENCY := 0 223 224# Set the default algorithm for the generation of Trusted Board Boot keys 225KEY_ALG := rsa 226 227# Set the default key size in case KEY_ALG is rsa 228ifeq ($(KEY_ALG),rsa) 229KEY_SIZE := 2048 230endif 231 232# Option to build TF with Measured Boot support 233MEASURED_BOOT := 0 234 235# NS timer register save and restore 236NS_TIMER_SWITCH := 0 237 238# Include lib/libc in the final image 239OVERRIDE_LIBC := 0 240 241# Build PL011 UART driver in minimal generic UART mode 242PL011_GENERIC_UART := 0 243 244# By default, consider that the platform's reset address is not programmable. 245# The platform Makefile is free to override this value. 246PROGRAMMABLE_RESET_ADDRESS := 0 247 248# Flag used to choose the power state format: Extended State-ID or Original 249PSCI_EXTENDED_STATE_ID := 0 250 251# Enable RAS support 252RAS_EXTENSION := 0 253 254# By default, BL1 acts as the reset handler, not BL31 255RESET_TO_BL31 := 0 256 257# For Chain of Trust 258SAVE_KEYS := 0 259 260# Software Delegated Exception support 261SDEI_SUPPORT := 0 262 263# True Random Number firmware Interface 264TRNG_SUPPORT := 0 265 266# SMCCC PCI support 267SMC_PCI_SUPPORT := 0 268 269# Whether code and read-only data should be put on separate memory pages. The 270# platform Makefile is free to override this value. 271SEPARATE_CODE_AND_RODATA := 0 272 273# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 274# separate memory region, which may be discontiguous from the rest of BL31. 275SEPARATE_NOBITS_REGION := 0 276 277# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 278# region, platform Makefile is free to override this value. 279SEPARATE_BL2_NOLOAD_REGION := 0 280 281# If the BL31 image initialisation code is recalimed after use for the secondary 282# cores stack 283RECLAIM_INIT_CODE := 0 284 285# SPD choice 286SPD := none 287 288# Enable the Management Mode (MM)-based Secure Partition Manager implementation 289SPM_MM := 0 290 291# Use SPM at S-EL2 as a default config for SPMD 292SPMD_SPM_AT_SEL2 := 1 293 294# Flag to introduce an infinite loop in BL1 just before it exits into the next 295# image. This is meant to help debugging the post-BL2 phase. 296SPIN_ON_BL1_EXIT := 0 297 298# Flags to build TF with Trusted Boot support 299TRUSTED_BOARD_BOOT := 0 300 301# Build option to choose whether Trusted Firmware uses Coherent memory or not. 302USE_COHERENT_MEM := 1 303 304# Build option to add debugfs support 305USE_DEBUGFS := 0 306 307# Build option to fconf based io 308ARM_IO_IN_DTB := 0 309 310# Build option to support SDEI through fconf 311SDEI_IN_FCONF := 0 312 313# Build option to support Secure Interrupt descriptors through fconf 314SEC_INT_DESC_IN_FCONF := 0 315 316# Build option to choose whether Trusted Firmware uses library at ROM 317USE_ROMLIB := 0 318 319# Build option to choose whether the xlat tables of BL images can be read-only. 320# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 321# which is the per BL-image option that actually enables the read-only tables 322# API. The reason for having this additional option is to have a common high 323# level makefile where we can check for incompatible features/build options. 324ALLOW_RO_XLAT_TABLES := 0 325 326# Chain of trust. 327COT := tbbr 328 329# Use tbbr_oid.h instead of platform_oid.h 330USE_TBBR_DEFS := 1 331 332# Build verbosity 333V := 0 334 335# Whether to enable D-Cache early during warm boot. This is usually 336# applicable for platforms wherein interconnect programming is not 337# required to enable cache coherency after warm reset (eg: single cluster 338# platforms). 339WARMBOOT_ENABLE_DCACHE_EARLY := 0 340 341# Build option to enable/disable the Statistical Profiling Extensions 342ENABLE_SPE_FOR_LOWER_ELS := 1 343 344# SPE is only supported on AArch64 so disable it on AArch32. 345ifeq (${ARCH},aarch32) 346 override ENABLE_SPE_FOR_LOWER_ELS := 0 347endif 348 349# Include Memory Tagging Extension registers in cpu context. This must be set 350# to 1 if the platform wants to use this feature in the Secure world and MTE is 351# enabled at ELX. 352CTX_INCLUDE_MTE_REGS := 0 353 354ENABLE_AMU := 0 355ENABLE_AMU_AUXILIARY_COUNTERS := 0 356ENABLE_AMU_FCONF := 0 357AMU_RESTRICT_COUNTERS := 0 358 359# Enable SVE for non-secure world by default 360ENABLE_SVE_FOR_NS := 1 361# SVE is only supported on AArch64 so disable it on AArch32. 362ifeq (${ARCH},aarch32) 363 override ENABLE_SVE_FOR_NS := 0 364endif 365ENABLE_SVE_FOR_SWD := 0 366 367# SME defaults to disabled 368ENABLE_SME_FOR_NS := 0 369ENABLE_SME_FOR_SWD := 0 370 371# If SME is enabled then force SVE off 372ifeq (${ENABLE_SME_FOR_NS},1) 373 override ENABLE_SVE_FOR_NS := 0 374 override ENABLE_SVE_FOR_SWD := 0 375endif 376 377SANITIZE_UB := off 378 379# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 380# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 381# Default: disabled 382USE_SPINLOCK_CAS := 0 383 384# Enable Link Time Optimization 385ENABLE_LTO := 0 386 387# Build flag to include EL2 registers in cpu context save and restore during 388# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 389# Default is 0. 390CTX_INCLUDE_EL2_REGS := 0 391 392# Enable Memory tag extension which is supported for architecture greater 393# than Armv8.5-A 394# By default it is set to "no" 395SUPPORT_STACK_MEMTAG := no 396 397# Select workaround for AT speculative behaviour. 398ERRATA_SPECULATIVE_AT := 0 399 400# Trap RAS error record access from lower EL 401RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 402 403# Build option to create cot descriptors using fconf 404COT_DESC_IN_DTB := 0 405 406# Build option to provide openssl directory path 407OPENSSL_DIR := /usr 408 409# Build option to use the SP804 timer instead of the generic one 410USE_SP804_TIMER := 0 411 412# Build option to define number of firmware banks, used in firmware update 413# metadata structure. 414NR_OF_FW_BANKS := 2 415 416# Build option to define number of images in firmware bank, used in firmware 417# update metadata structure. 418NR_OF_IMAGES_IN_FW_BANK := 1 419 420# Disable Firmware update support by default 421PSA_FWU_SUPPORT := 0 422 423# By default, disable access of trace buffer control registers from NS 424# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 425# if FEAT_TRBE is implemented. 426# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 427# AArch32. 428ifneq (${ARCH},aarch32) 429 ENABLE_TRBE_FOR_NS := 0 430else 431 override ENABLE_TRBE_FOR_NS := 0 432endif 433 434# By default, disable access of trace system registers from NS lower 435# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 436# system register trace is implemented. 437ENABLE_SYS_REG_TRACE_FOR_NS := 0 438 439# By default, disable trace filter control registers access to NS 440# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 441# if FEAT_TRF is implemented. 442ENABLE_TRF_FOR_NS := 0 443