1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# Execute BL2 at EL3 31BL2_AT_EL3 := 0 32 33# BL2 image is stored in XIP memory, for now, this option is only supported 34# when BL2_AT_EL3 is 1. 35BL2_IN_XIP_MEM := 0 36 37# By default, consider that the platform may release several CPUs out of reset. 38# The platform Makefile is free to override this value. 39COLD_BOOT_SINGLE_CPU := 0 40 41# Flag to compile in coreboot support code. Exclude by default. The coreboot 42# Makefile system will set this when compiling TF as part of a coreboot image. 43COREBOOT := 0 44 45# For Chain of Trust 46CREATE_KEYS := 1 47 48# Build flag to include AArch32 registers in cpu context save and restore during 49# world switch. This flag must be set to 0 for AArch64-only platforms. 50CTX_INCLUDE_AARCH32_REGS := 1 51 52# Include FP registers in cpu context 53CTX_INCLUDE_FPREGS := 0 54 55# Debug build 56DEBUG := 0 57 58# Build platform 59DEFAULT_PLAT := fvp 60 61# Flag to enable Performance Measurement Framework 62ENABLE_PMF := 0 63 64# Flag to enable PSCI STATs functionality 65ENABLE_PSCI_STAT := 0 66 67# Flag to enable runtime instrumentation using PMF 68ENABLE_RUNTIME_INSTRUMENTATION := 0 69 70# Flag to enable stack corruption protection 71ENABLE_STACK_PROTECTOR := 0 72 73# Flag to enable exception handling in EL3 74EL3_EXCEPTION_HANDLING := 0 75 76# Build flag to treat usage of deprecated platform and framework APIs as error. 77ERROR_DEPRECATED := 0 78 79# Byte alignment that each component in FIP is aligned to 80FIP_ALIGN := 0 81 82# Default FIP file name 83FIP_NAME := fip.bin 84 85# Default FWU_FIP file name 86FWU_FIP_NAME := fwu_fip.bin 87 88# For Chain of Trust 89GENERATE_COT := 0 90 91# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 92# default, they are for Secure EL1. 93GICV2_G0_FOR_EL3 := 0 94 95# Whether system coherency is managed in hardware, without explicit software 96# operations. 97HW_ASSISTED_COHERENCY := 0 98 99# Set the default algorithm for the generation of Trusted Board Boot keys 100KEY_ALG := rsa 101 102# Flag to enable new version of image loading 103LOAD_IMAGE_V2 := 0 104 105# Enable use of the console API allowing multiple consoles to be registered 106# at the same time. 107MULTI_CONSOLE_API := 0 108 109# NS timer register save and restore 110NS_TIMER_SWITCH := 0 111 112# Build PL011 UART driver in minimal generic UART mode 113PL011_GENERIC_UART := 0 114 115# By default, consider that the platform's reset address is not programmable. 116# The platform Makefile is free to override this value. 117PROGRAMMABLE_RESET_ADDRESS := 0 118 119# Flag used to choose the power state format viz Extended State-ID or the 120# Original format. 121PSCI_EXTENDED_STATE_ID := 0 122 123# By default, BL1 acts as the reset handler, not BL31 124RESET_TO_BL31 := 0 125 126# For Chain of Trust 127SAVE_KEYS := 0 128 129# Software Delegated Exception support 130SDEI_SUPPORT := 0 131 132# Whether code and read-only data should be put on separate memory pages. The 133# platform Makefile is free to override this value. 134SEPARATE_CODE_AND_RODATA := 0 135 136# Default to SMCCC Version 1.X 137SMCCC_MAJOR_VERSION := 1 138 139# SPD choice 140SPD := none 141 142# For including the Secure Partition Manager 143ENABLE_SPM := 0 144 145# Flag to introduce an infinite loop in BL1 just before it exits into the next 146# image. This is meant to help debugging the post-BL2 phase. 147SPIN_ON_BL1_EXIT := 0 148 149# Flags to build TF with Trusted Boot support 150TRUSTED_BOARD_BOOT := 0 151 152# Build option to choose whether Trusted firmware uses Coherent memory or not. 153USE_COHERENT_MEM := 1 154 155# Use tbbr_oid.h instead of platform_oid.h 156USE_TBBR_DEFS = $(ERROR_DEPRECATED) 157 158# Build verbosity 159V := 0 160 161# Whether to enable D-Cache early during warm boot. This is usually 162# applicable for platforms wherein interconnect programming is not 163# required to enable cache coherency after warm reset (eg: single cluster 164# platforms). 165WARMBOOT_ENABLE_DCACHE_EARLY := 0 166 167# Build option to enable/disable the Statistical Profiling Extensions 168ENABLE_SPE_FOR_LOWER_ELS := 1 169 170# SPE is only supported on AArch64 so disable it on AArch32. 171ifeq (${ARCH},aarch32) 172 override ENABLE_SPE_FOR_LOWER_ELS := 0 173endif 174 175ENABLE_AMU := 0 176 177# By default, enable Scalable Vector Extension if implemented for Non-secure 178# lower ELs 179# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 180ifneq (${ARCH},aarch32) 181 ENABLE_SVE_FOR_NS := 1 182else 183 override ENABLE_SVE_FOR_NS := 0 184endif 185