xref: /rk3399_ARM-atf/make_helpers/defaults.mk (revision d4c596be87e0b04404fc10ee49544eda33c0f625)
1#
2# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP			:= none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH				:= aarch64
18
19# ARM Architecture major and minor versions: 8.0 by default.
20ARM_ARCH_MAJOR			:= 8
21ARM_ARCH_MINOR			:= 0
22
23# Determine the version of ARM GIC architecture to use for interrupt management
24# in EL3. The platform port can change this value if needed.
25ARM_GIC_ARCH			:= 2
26
27# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
28ASM_ASSERTION			:= 0
29
30# Base commit to perform code check on
31BASE_COMMIT			:= origin/master
32
33# By default, consider that the platform may release several CPUs out of reset.
34# The platform Makefile is free to override this value.
35COLD_BOOT_SINGLE_CPU		:= 0
36
37# For Chain of Trust
38CREATE_KEYS			:= 1
39
40# Build flag to include AArch32 registers in cpu context save and restore during
41# world switch. This flag must be set to 0 for AArch64-only platforms.
42CTX_INCLUDE_AARCH32_REGS	:= 1
43
44# Include FP registers in cpu context
45CTX_INCLUDE_FPREGS		:= 0
46
47# Debug build
48DEBUG				:= 0
49
50# Build platform
51DEFAULT_PLAT			:= fvp
52
53# Flag to enable Performance Measurement Framework
54ENABLE_PMF			:= 0
55
56# Flag to enable PSCI STATs functionality
57ENABLE_PSCI_STAT		:= 0
58
59# Flag to enable runtime instrumentation using PMF
60ENABLE_RUNTIME_INSTRUMENTATION	:= 0
61
62# Flag to enable stack corruption protection
63ENABLE_STACK_PROTECTOR		:= 0
64
65# Build flag to treat usage of deprecated platform and framework APIs as error.
66ERROR_DEPRECATED		:= 0
67
68# Byte alignment that each component in FIP is aligned to
69FIP_ALIGN			:= 0
70
71# Default FIP file name
72FIP_NAME			:= fip.bin
73
74# Default FWU_FIP file name
75FWU_FIP_NAME			:= fwu_fip.bin
76
77# For Chain of Trust
78GENERATE_COT			:= 0
79
80# Whether system coherency is managed in hardware, without explicit software
81# operations.
82HW_ASSISTED_COHERENCY		:= 0
83
84# Set the default algorithm for the generation of Trusted Board Boot keys
85KEY_ALG				:= rsa
86
87# Flag to enable new version of image loading
88LOAD_IMAGE_V2			:= 0
89
90# NS timer register save and restore
91NS_TIMER_SWITCH			:= 0
92
93# Build PL011 UART driver in minimal generic UART mode
94PL011_GENERIC_UART		:= 0
95
96# By default, consider that the platform's reset address is not programmable.
97# The platform Makefile is free to override this value.
98PROGRAMMABLE_RESET_ADDRESS	:= 0
99
100# Flag used to choose the power state format viz Extended State-ID or the
101# Original format.
102PSCI_EXTENDED_STATE_ID		:= 0
103
104# By default, BL1 acts as the reset handler, not BL31
105RESET_TO_BL31			:= 0
106
107# For Chain of Trust
108SAVE_KEYS			:= 0
109
110# Whether code and read-only data should be put on separate memory pages. The
111# platform Makefile is free to override this value.
112SEPARATE_CODE_AND_RODATA	:= 0
113
114# SPD choice
115SPD				:= none
116
117# Flag to introduce an infinite loop in BL1 just before it exits into the next
118# image. This is meant to help debugging the post-BL2 phase.
119SPIN_ON_BL1_EXIT		:= 0
120
121# Flags to build TF with Trusted Boot support
122TRUSTED_BOARD_BOOT		:= 0
123
124# Build option to choose whether Trusted firmware uses Coherent memory or not.
125USE_COHERENT_MEM		:= 1
126
127# Use tbbr_oid.h instead of platform_oid.h
128USE_TBBR_DEFS			= $(ERROR_DEPRECATED)
129
130# Build verbosity
131V				:= 0
132
133# Whether to enable D-Cache early during warm boot. This is usually
134# applicable for platforms wherein interconnect programming is not
135# required to enable cache coherency after warm reset (eg: single cluster
136# platforms).
137WARMBOOT_ENABLE_DCACHE_EARLY	:= 0
138
139# By default, enable Statistical Profiling Extensions.
140# The top level Makefile will disable this feature depending on
141# the target architecture and version number.
142ENABLE_SPE_FOR_LOWER_ELS	:= 1
143
144# SPE is enabled by default but only supported on AArch64 8.2 onwards.
145# Disable it in all other cases.
146ifeq (${ARCH},aarch32)
147    override ENABLE_SPE_FOR_LOWER_ELS := 0
148else
149    ifeq (${ARM_ARCH_MAJOR},8)
150        ifeq ($(ARM_ARCH_MINOR),$(filter $(ARM_ARCH_MINOR),0 1))
151            ENABLE_SPE_FOR_LOWER_ELS := 0
152        endif
153    endif
154endif
155