1# 2# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# Select the branch protection features to use. 37BRANCH_PROTECTION := 0 38 39# By default, consider that the platform may release several CPUs out of reset. 40# The platform Makefile is free to override this value. 41COLD_BOOT_SINGLE_CPU := 0 42 43# Flag to compile in coreboot support code. Exclude by default. The coreboot 44# Makefile system will set this when compiling TF as part of a coreboot image. 45COREBOOT := 0 46 47# For Chain of Trust 48CREATE_KEYS := 1 49 50# Build flag to include AArch32 registers in cpu context save and restore during 51# world switch. This flag must be set to 0 for AArch64-only platforms. 52CTX_INCLUDE_AARCH32_REGS := 1 53 54# Include FP registers in cpu context 55CTX_INCLUDE_FPREGS := 0 56 57# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 58# must be set to 1 if the platform wants to use this feature in the Secure 59# world. It is not needed to use it in the Non-secure world. 60CTX_INCLUDE_PAUTH_REGS := 0 61 62# Debug build 63DEBUG := 0 64 65# Build platform 66DEFAULT_PLAT := fvp 67 68# Disable the generation of the binary image (ELF only). 69DISABLE_BIN_GENERATION := 0 70 71# Enable capability to disable authentication dynamically. Only meant for 72# development platforms. 73DYN_DISABLE_AUTH := 0 74 75# Build option to enable MPAM for lower ELs 76ENABLE_MPAM_FOR_LOWER_ELS := 0 77 78# Flag to Enable Position Independant support (PIE) 79ENABLE_PIE := 0 80 81# Flag to enable Performance Measurement Framework 82ENABLE_PMF := 0 83 84# Flag to enable PSCI STATs functionality 85ENABLE_PSCI_STAT := 0 86 87# Flag to enable runtime instrumentation using PMF 88ENABLE_RUNTIME_INSTRUMENTATION := 0 89 90# Flag to enable stack corruption protection 91ENABLE_STACK_PROTECTOR := 0 92 93# Flag to enable exception handling in EL3 94EL3_EXCEPTION_HANDLING := 0 95 96# Flag to enable Branch Target Identification. 97# Internal flag not meant for direct setting. 98# Use BRANCH_PROTECTION to enable BTI. 99ENABLE_BTI := 0 100 101# Flag to enable Pointer Authentication. 102# Internal flag not meant for direct setting. 103# Use BRANCH_PROTECTION to enable PAUTH. 104ENABLE_PAUTH := 0 105 106# Build flag to treat usage of deprecated platform and framework APIs as error. 107ERROR_DEPRECATED := 0 108 109# Fault injection support 110FAULT_INJECTION_SUPPORT := 0 111 112# Byte alignment that each component in FIP is aligned to 113FIP_ALIGN := 0 114 115# Default FIP file name 116FIP_NAME := fip.bin 117 118# Default FWU_FIP file name 119FWU_FIP_NAME := fwu_fip.bin 120 121# For Chain of Trust 122GENERATE_COT := 0 123 124# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 125# default, they are for Secure EL1. 126GICV2_G0_FOR_EL3 := 0 127 128# Route External Aborts to EL3. Disabled by default; External Aborts are handled 129# by lower ELs. 130HANDLE_EA_EL3_FIRST := 0 131 132# Whether system coherency is managed in hardware, without explicit software 133# operations. 134HW_ASSISTED_COHERENCY := 0 135 136# Set the default algorithm for the generation of Trusted Board Boot keys 137KEY_ALG := rsa 138 139# Enable use of the console API allowing multiple consoles to be registered 140# at the same time. 141MULTI_CONSOLE_API := 0 142 143# NS timer register save and restore 144NS_TIMER_SWITCH := 0 145 146# Include lib/libc in the final image 147OVERRIDE_LIBC := 0 148 149# Build PL011 UART driver in minimal generic UART mode 150PL011_GENERIC_UART := 0 151 152# By default, consider that the platform's reset address is not programmable. 153# The platform Makefile is free to override this value. 154PROGRAMMABLE_RESET_ADDRESS := 0 155 156# Flag used to choose the power state format: Extended State-ID or Original 157PSCI_EXTENDED_STATE_ID := 0 158 159# Enable RAS support 160RAS_EXTENSION := 0 161 162# By default, BL1 acts as the reset handler, not BL31 163RESET_TO_BL31 := 0 164 165# For Chain of Trust 166SAVE_KEYS := 0 167 168# Software Delegated Exception support 169SDEI_SUPPORT := 0 170 171# Whether code and read-only data should be put on separate memory pages. The 172# platform Makefile is free to override this value. 173SEPARATE_CODE_AND_RODATA := 0 174 175# If the BL31 image initialisation code is recalimed after use for the secondary 176# cores stack 177RECLAIM_INIT_CODE := 0 178 179# SPD choice 180SPD := none 181 182# For including the Secure Partition Manager 183ENABLE_SPM := 0 184 185# Use the SPM based on MM 186SPM_MM := 1 187 188# Flag to introduce an infinite loop in BL1 just before it exits into the next 189# image. This is meant to help debugging the post-BL2 phase. 190SPIN_ON_BL1_EXIT := 0 191 192# Flags to build TF with Trusted Boot support 193TRUSTED_BOARD_BOOT := 0 194 195# Build option to choose whether Trusted Firmware uses Coherent memory or not. 196USE_COHERENT_MEM := 1 197 198# Build option to choose whether Trusted Firmware uses library at ROM 199USE_ROMLIB := 0 200 201# Use tbbr_oid.h instead of platform_oid.h 202USE_TBBR_DEFS := 1 203 204# Build verbosity 205V := 0 206 207# Whether to enable D-Cache early during warm boot. This is usually 208# applicable for platforms wherein interconnect programming is not 209# required to enable cache coherency after warm reset (eg: single cluster 210# platforms). 211WARMBOOT_ENABLE_DCACHE_EARLY := 0 212 213# Build option to enable/disable the Statistical Profiling Extensions 214ENABLE_SPE_FOR_LOWER_ELS := 1 215 216# SPE is only supported on AArch64 so disable it on AArch32. 217ifeq (${ARCH},aarch32) 218 override ENABLE_SPE_FOR_LOWER_ELS := 0 219endif 220 221ENABLE_AMU := 0 222 223# By default, enable Scalable Vector Extension if implemented for Non-secure 224# lower ELs 225# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 226ifneq (${ARCH},aarch32) 227 ENABLE_SVE_FOR_NS := 1 228else 229 override ENABLE_SVE_FOR_NS := 0 230endif 231