1# 2# Copyright (c) 2016-2020, ARM Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# Do dcache invalidate upon BL2 entry at EL3 37BL2_INV_DCACHE := 1 38 39# Select the branch protection features to use. 40BRANCH_PROTECTION := 0 41 42# By default, consider that the platform may release several CPUs out of reset. 43# The platform Makefile is free to override this value. 44COLD_BOOT_SINGLE_CPU := 0 45 46# Flag to compile in coreboot support code. Exclude by default. The coreboot 47# Makefile system will set this when compiling TF as part of a coreboot image. 48COREBOOT := 0 49 50# For Chain of Trust 51CREATE_KEYS := 1 52 53# Build flag to include AArch32 registers in cpu context save and restore during 54# world switch. This flag must be set to 0 for AArch64-only platforms. 55CTX_INCLUDE_AARCH32_REGS := 1 56 57# Include FP registers in cpu context 58CTX_INCLUDE_FPREGS := 0 59 60# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 61# must be set to 1 if the platform wants to use this feature in the Secure 62# world. It is not needed to use it in the Non-secure world. 63CTX_INCLUDE_PAUTH_REGS := 0 64 65# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 66# This must be set to 1 if architecture implements Nested Virtualization 67# Extension and platform wants to use this feature in the Secure world 68CTX_INCLUDE_NEVE_REGS := 0 69 70# Debug build 71DEBUG := 0 72 73# By default disable authenticated decryption support. 74DECRYPTION_SUPPORT := none 75 76# Build platform 77DEFAULT_PLAT := fvp 78 79# Disable the generation of the binary image (ELF only). 80DISABLE_BIN_GENERATION := 0 81 82# Enable capability to disable authentication dynamically. Only meant for 83# development platforms. 84DYN_DISABLE_AUTH := 0 85 86# Build option to enable MPAM for lower ELs 87ENABLE_MPAM_FOR_LOWER_ELS := 0 88 89# Flag to Enable Position Independant support (PIE) 90ENABLE_PIE := 0 91 92# Flag to enable Performance Measurement Framework 93ENABLE_PMF := 0 94 95# Flag to enable PSCI STATs functionality 96ENABLE_PSCI_STAT := 0 97 98# Flag to enable runtime instrumentation using PMF 99ENABLE_RUNTIME_INSTRUMENTATION := 0 100 101# Flag to enable stack corruption protection 102ENABLE_STACK_PROTECTOR := 0 103 104# Flag to enable exception handling in EL3 105EL3_EXCEPTION_HANDLING := 0 106 107# Flag to enable Branch Target Identification. 108# Internal flag not meant for direct setting. 109# Use BRANCH_PROTECTION to enable BTI. 110ENABLE_BTI := 0 111 112# Flag to enable Pointer Authentication. 113# Internal flag not meant for direct setting. 114# Use BRANCH_PROTECTION to enable PAUTH. 115ENABLE_PAUTH := 0 116 117# By default BL31 encryption disabled 118ENCRYPT_BL31 := 0 119 120# By default BL32 encryption disabled 121ENCRYPT_BL32 := 0 122 123# Default dummy firmware encryption key 124ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 125 126# Default dummy nonce for firmware encryption 127ENC_NONCE := 1234567890abcdef12345678 128 129# Build flag to treat usage of deprecated platform and framework APIs as error. 130ERROR_DEPRECATED := 0 131 132# Fault injection support 133FAULT_INJECTION_SUPPORT := 0 134 135# Byte alignment that each component in FIP is aligned to 136FIP_ALIGN := 0 137 138# Default FIP file name 139FIP_NAME := fip.bin 140 141# Default FWU_FIP file name 142FWU_FIP_NAME := fwu_fip.bin 143 144# By default firmware encryption with SSK 145FW_ENC_STATUS := 0 146 147# For Chain of Trust 148GENERATE_COT := 0 149 150# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 151# default, they are for Secure EL1. 152GICV2_G0_FOR_EL3 := 0 153 154# Route External Aborts to EL3. Disabled by default; External Aborts are handled 155# by lower ELs. 156HANDLE_EA_EL3_FIRST := 0 157 158# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 159# The default value is sha256. 160HASH_ALG := sha256 161 162# Whether system coherency is managed in hardware, without explicit software 163# operations. 164HW_ASSISTED_COHERENCY := 0 165 166# Set the default algorithm for the generation of Trusted Board Boot keys 167KEY_ALG := rsa 168 169# Set the default key size in case KEY_ALG is rsa 170ifeq ($(KEY_ALG),rsa) 171KEY_SIZE := 2048 172endif 173 174# Option to build TF with Measured Boot support 175MEASURED_BOOT := 0 176 177# NS timer register save and restore 178NS_TIMER_SWITCH := 0 179 180# Include lib/libc in the final image 181OVERRIDE_LIBC := 0 182 183# Build PL011 UART driver in minimal generic UART mode 184PL011_GENERIC_UART := 0 185 186# By default, consider that the platform's reset address is not programmable. 187# The platform Makefile is free to override this value. 188PROGRAMMABLE_RESET_ADDRESS := 0 189 190# Flag used to choose the power state format: Extended State-ID or Original 191PSCI_EXTENDED_STATE_ID := 0 192 193# Enable RAS support 194RAS_EXTENSION := 0 195 196# By default, BL1 acts as the reset handler, not BL31 197RESET_TO_BL31 := 0 198 199# For Chain of Trust 200SAVE_KEYS := 0 201 202# Software Delegated Exception support 203SDEI_SUPPORT := 0 204 205# Whether code and read-only data should be put on separate memory pages. The 206# platform Makefile is free to override this value. 207SEPARATE_CODE_AND_RODATA := 0 208 209# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 210# separate memory region, which may be discontiguous from the rest of BL31. 211SEPARATE_NOBITS_REGION := 0 212 213# If the BL31 image initialisation code is recalimed after use for the secondary 214# cores stack 215RECLAIM_INIT_CODE := 0 216 217# SPD choice 218SPD := none 219 220# Enable the Management Mode (MM)-based Secure Partition Manager implementation 221SPM_MM := 0 222 223# Use SPM at S-EL2 as a default config for SPMD 224SPMD_SPM_AT_SEL2 := 1 225 226# Flag to introduce an infinite loop in BL1 just before it exits into the next 227# image. This is meant to help debugging the post-BL2 phase. 228SPIN_ON_BL1_EXIT := 0 229 230# Flags to build TF with Trusted Boot support 231TRUSTED_BOARD_BOOT := 0 232 233# Build option to choose whether Trusted Firmware uses Coherent memory or not. 234USE_COHERENT_MEM := 1 235 236# Build option to add debugfs support 237USE_DEBUGFS := 0 238 239# Build option to fconf based io 240ARM_IO_IN_DTB := 0 241 242# Build option to support SDEI through fconf 243SDEI_IN_FCONF := 0 244 245# Build option to support Secure Interrupt descriptors through fconf 246SEC_INT_DESC_IN_FCONF := 0 247 248# Build option to choose whether Trusted Firmware uses library at ROM 249USE_ROMLIB := 0 250 251# Build option to choose whether the xlat tables of BL images can be read-only. 252# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 253# which is the per BL-image option that actually enables the read-only tables 254# API. The reason for having this additional option is to have a common high 255# level makefile where we can check for incompatible features/build options. 256ALLOW_RO_XLAT_TABLES := 0 257 258# Chain of trust. 259COT := tbbr 260 261# Use tbbr_oid.h instead of platform_oid.h 262USE_TBBR_DEFS := 1 263 264# Build verbosity 265V := 0 266 267# Whether to enable D-Cache early during warm boot. This is usually 268# applicable for platforms wherein interconnect programming is not 269# required to enable cache coherency after warm reset (eg: single cluster 270# platforms). 271WARMBOOT_ENABLE_DCACHE_EARLY := 0 272 273# Build option to enable/disable the Statistical Profiling Extensions 274ENABLE_SPE_FOR_LOWER_ELS := 1 275 276# SPE is only supported on AArch64 so disable it on AArch32. 277ifeq (${ARCH},aarch32) 278 override ENABLE_SPE_FOR_LOWER_ELS := 0 279endif 280 281# Include Memory Tagging Extension registers in cpu context. This must be set 282# to 1 if the platform wants to use this feature in the Secure world and MTE is 283# enabled at ELX. 284CTX_INCLUDE_MTE_REGS := 0 285 286ENABLE_AMU := 0 287 288# By default, enable Scalable Vector Extension if implemented for Non-secure 289# lower ELs 290# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 291ifneq (${ARCH},aarch32) 292 ENABLE_SVE_FOR_NS := 1 293else 294 override ENABLE_SVE_FOR_NS := 0 295endif 296 297SANITIZE_UB := off 298 299# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 300# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 301# Default: disabled 302USE_SPINLOCK_CAS := 0 303 304# Enable Link Time Optimization 305ENABLE_LTO := 0 306 307# Build flag to include EL2 registers in cpu context save and restore during 308# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 309# Default is 0. 310CTX_INCLUDE_EL2_REGS := 0 311 312# Enable Memory tag extension which is supported for architecture greater 313# than Armv8.5-A 314# By default it is set to "no" 315SUPPORT_STACK_MEMTAG := no 316 317# Select workaround for AT speculative behaviour. 318ERRATA_SPECULATIVE_AT := 0 319 320# Trap RAS error record access from lower EL 321RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 322 323# Build option to create cot descriptors using fconf 324COT_DESC_IN_DTB := 0 325 326# Build option to provide openssl directory path 327OPENSSL_DIR := /usr 328 329# Build option to use the SP804 timer instead of the generic one 330USE_SP804_TIMER := 0 331