1# 2# Copyright (c) 2016-2026, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Warning level to give to the compiler 14W := 0 15 16# Use T32 by default 17AARCH32_INSTRUCTION_SET := T32 18 19# The AArch32 Secure Payload to be built as BL32 image 20AARCH32_SP := none 21 22# The Target build architecture. Supported values are: aarch64, aarch32. 23ARCH := aarch64 24 25# ARM Architecture feature modifiers: none by default 26ARM_ARCH_FEATURE := none 27 28# ARM Architecture major and minor versions: 8.0 by default. 29ARM_ARCH_MAJOR := 8 30ARM_ARCH_MINOR := 0 31 32# Base commit to perform code check on 33BASE_COMMIT := origin/master 34 35# Execute BL2 at EL3 36RESET_TO_BL2 := 0 37 38# Only use SP packages if SP layout JSON is defined 39BL2_ENABLE_SP_LOAD := 0 40 41# BL2 image is stored in XIP memory, for now, this option is only supported 42# when RESET_TO_BL2 is 1. 43BL2_IN_XIP_MEM := 0 44 45# Do dcache invalidate upon BL2 entry at EL3 46BL2_INV_DCACHE := 1 47 48# Select the branch protection features to use. 49BRANCH_PROTECTION := 0 50 51# By default, consider that the platform may release several CPUs out of reset. 52# The platform Makefile is free to override this value. 53COLD_BOOT_SINGLE_CPU := 0 54 55# Flag to compile in coreboot support code. Exclude by default. The coreboot 56# Makefile system will set this when compiling TF as part of a coreboot image. 57COREBOOT := 0 58 59# For Chain of Trust 60CREATE_KEYS := 1 61 62# Build flag to include AArch32 registers in cpu context save and restore during 63# world switch. This flag must be set to 0 for AArch64-only platforms. 64CTX_INCLUDE_AARCH32_REGS := 1 65 66# Include FP registers in cpu context 67CTX_INCLUDE_FPREGS := 0 68 69# Include SVE registers in cpu context 70CTX_INCLUDE_SVE_REGS := 0 71 72# Debug build 73DEBUG := 0 74 75# By default disable authenticated decryption support. 76DECRYPTION_SUPPORT := none 77 78# Build platform 79DEFAULT_PLAT := fvp 80 81# Disable the generation of the binary image (ELF only). 82DISABLE_BIN_GENERATION := 0 83 84# Enable capability to disable authentication dynamically. Only meant for 85# development platforms. 86DYN_DISABLE_AUTH := 0 87 88# Enable the SIMD crypto extension feature. The flags suppose to be in 89# arch_features.mk but since mbedtls_common.mk is included before arch_features.mk, 90# so this flag has to be defined here. 91ENABLE_FEAT_CRYPTO := 0 92 93# Enable the SIMD SHA3 crypto extension feature. 94ENABLE_FEAT_CRYPTO_SHA3 := 0 95 96# Enable the Maximum Power Mitigation Mechanism on supporting cores. 97ENABLE_MPMM := 0 98 99# Flag to Enable Position Independant support (PIE) 100ENABLE_PIE := 0 101 102# Flag to enable Performance Measurement Framework 103ENABLE_PMF := 0 104 105# Flag to enable PSCI STATs functionality 106ENABLE_PSCI_STAT := 0 107 108# Flag to enable runtime instrumentation using PMF 109ENABLE_RUNTIME_INSTRUMENTATION := 0 110 111# Flag to enable stack corruption protection 112ENABLE_STACK_PROTECTOR := 0 113 114# Flag to enable exception handling in EL3 115EL3_EXCEPTION_HANDLING := 0 116 117# Flag to include all errata for all CPUs TF-A implements workarounds for 118# Its supposed to be used only for testing. 119ENABLE_ERRATA_ALL := 0 120 121# By default BL31 encryption disabled 122ENCRYPT_BL31 := 0 123 124# By default BL32 encryption disabled 125ENCRYPT_BL32 := 0 126 127# Default dummy firmware encryption key 128ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 129 130# Default dummy nonce for firmware encryption 131ENC_NONCE := 1234567890abcdef12345678 132 133# Build flag to treat usage of deprecated platform and framework APIs as error. 134ERROR_DEPRECATED := 0 135 136# Fault injection support 137FAULT_INJECTION_SUPPORT := 0 138 139# Flag to enable architectural features detection mechanism 140FEATURE_DETECTION := 0 141 142# Byte alignment that each component in FIP is aligned to 143FIP_ALIGN := 0 144 145# Default FIP file name 146FIP_NAME := fip.bin 147 148# Default FWU_FIP file name 149FWU_FIP_NAME := fwu_fip.bin 150 151# Default BL2 FIP file name 152BL2_FIP_NAME := bl2_fip.bin 153 154# By default firmware encryption with SSK 155FW_ENC_STATUS := 0 156 157# For Chain of Trust 158GENERATE_COT := 0 159 160# Default number of 512 blocks per bitlock 161RME_GPT_BITLOCK_BLOCK := 1 162 163# Default maximum size of GPT contiguous block 164RME_GPT_MAX_BLOCK := 512 165 166# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 167# default, they are for Secure EL1. 168GICV2_G0_FOR_EL3 := 0 169 170# Generic implementation of a GICvX driver 171USE_GIC_DRIVER := 0 172 173# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 174# by lower ELs. 175HANDLE_EA_EL3_FIRST_NS := 0 176 177# Enable Handoff protocol using transfer lists 178TRANSFER_LIST := 0 179 180# Enable HOB list to generate boot information 181HOB_LIST := 0 182 183# Enables support for the gcc compiler option "-mharden-sls=all". 184# By default, disables all SLS hardening. 185HARDEN_SLS := 0 186 187# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 188# The default value is sha256. 189HASH_ALG := sha256 190 191# Whether system coherency is managed in hardware, without explicit software 192# operations. 193HW_ASSISTED_COHERENCY := 0 194 195# Flag to enable trapping of implementation defined sytem registers 196IMPDEF_SYSREG_TRAP := 0 197 198# Set the default algorithm for the generation of Trusted Board Boot keys 199KEY_ALG := rsa 200 201# Set the default key size in case KEY_ALG is rsa 202ifeq ($(KEY_ALG),rsa) 203KEY_SIZE := 2048 204endif 205 206# Option to build TF with Measured Boot support 207MEASURED_BOOT := 0 208 209# Option to build TF with Discrete TPM support 210DISCRETE_TPM := 0 211 212# Option to enable the DICE Protection Environmnet as a Measured Boot backend 213DICE_PROTECTION_ENVIRONMENT :=0 214 215# NS timer register save and restore (deprecated) 216NS_TIMER_SWITCH := 0 217 218# Include lib/libc in the final image 219OVERRIDE_LIBC := 0 220 221# Build PL011 UART driver in minimal generic UART mode 222PL011_GENERIC_UART := 0 223 224# By default, consider that the platform's reset address is not programmable. 225# The platform Makefile is free to override this value. 226PROGRAMMABLE_RESET_ADDRESS := 0 227 228# Flag used to choose the power state format: Extended State-ID or Original 229PSCI_EXTENDED_STATE_ID := 0 230 231# Enable PSCI OS-initiated mode support 232PSCI_OS_INIT_MODE := 0 233 234# SMCCC_ARCH_FEATURE_AVAILABILITY support 235ARCH_FEATURE_AVAILABILITY := 0 236 237# By default, BL1 acts as the reset handler, not BL31 238RESET_TO_BL31 := 0 239 240# For Chain of Trust 241SAVE_KEYS := 0 242 243# Software Delegated Exception support 244SDEI_SUPPORT := 0 245 246# Number of UUIDs allowed for a physical partition 247SPMC_AT_EL3_PARTITION_MAX_UUIDS := 4 248 249# True Random Number firmware Interface support 250TRNG_SUPPORT := 0 251 252# Check to see if Errata ABI is supported 253ERRATA_ABI_SUPPORT := 0 254 255# Check to enable Errata ABI for platforms with non-arm interconnect 256ERRATA_NON_ARM_INTERCONNECT := 0 257 258# SMCCC PCI support 259SMC_PCI_SUPPORT := 0 260 261# Whether code and read-only data should be put on separate memory pages. The 262# platform Makefile is free to override this value. 263SEPARATE_CODE_AND_RODATA := 0 264 265# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 266# separate memory region, which may be discontiguous from the rest of BL31. 267SEPARATE_NOBITS_REGION := 0 268 269# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 270# region, platform Makefile is free to override this value. 271SEPARATE_BL2_NOLOAD_REGION := 0 272 273# Put RW DATA sections (.rwdata) in a separate memory region, which may be 274# discontiguous from the rest of BL31. 275SEPARATE_RWDATA_REGION := 0 276 277# Put SIMD context data structures in a separate memory region. Platforms 278# have the choice to put it outside of default BSS region of EL3 firmware. 279SEPARATE_SIMD_SECTION := 0 280 281# If the BL31 image initialisation code is recalimed after use for the secondary 282# cores stack 283RECLAIM_INIT_CODE := 0 284 285# SPD choice 286SPD := none 287 288# Enable the Management Mode (MM)-based Secure Partition Manager implementation 289SPM_MM := 0 290 291# Use the FF-A SPMC implementation in EL3. 292SPMC_AT_EL3 := 0 293 294# Enable SEL0 SP when SPMC is enabled at EL3 295SPMC_AT_EL3_SEL0_SP :=0 296 297# Use SPM at S-EL2 as a default config for SPMD 298SPMD_SPM_AT_SEL2 := 1 299 300# Flag to introduce an infinite loop in BL1 just before it exits into the next 301# image. This is meant to help debugging the post-BL2 phase. 302SPIN_ON_BL1_EXIT := 0 303 304# Flags to build TF with Trusted Boot support 305TRUSTED_BOARD_BOOT := 0 306 307# Build option to choose whether Trusted Firmware uses Coherent memory or not. 308USE_COHERENT_MEM := 1 309 310# Build option to add debugfs support 311USE_DEBUGFS := 0 312 313# Build option to enable passing the FDT in x0 to BL33, following the kernel 314# convention. 315USE_KERNEL_DT_CONVENTION := 0 316 317# Build option to fconf based io 318ARM_IO_IN_DTB := 0 319 320# Build option to support SDEI through fconf 321SDEI_IN_FCONF := 0 322 323# Build option to support Secure Interrupt descriptors through fconf 324SEC_INT_DESC_IN_FCONF := 0 325 326# Build option to choose whether Trusted Firmware uses library at ROM 327USE_ROMLIB := 0 328 329# Build option to choose whether the xlat tables of BL images can be read-only. 330# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 331# which is the per BL-image option that actually enables the read-only tables 332# API. The reason for having this additional option is to have a common high 333# level makefile where we can check for incompatible features/build options. 334ALLOW_RO_XLAT_TABLES := 0 335 336# Chain of trust. 337COT := tbbr 338 339# Use tbbr_oid.h instead of platform_oid.h 340USE_TBBR_DEFS := 1 341 342# Whether to enable D-Cache early during warm boot. This is usually 343# applicable for platforms wherein interconnect programming is not 344# required to enable cache coherency after warm reset (eg: single cluster 345# platforms). 346WARMBOOT_ENABLE_DCACHE_EARLY := 0 347 348# Default SVE vector length to maximum architected value 349SVE_VECTOR_LEN := 2048 350 351SANITIZE_UB := off 352 353# Enable Link Time Optimization 354ENABLE_LTO := 0 355 356# This option will include EL2 registers in cpu context save and restore during 357# EL2 firmware entry/exit. Internal flag not meant for direct setting. 358# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RMM=1 to enable 359# CTX_INCLUDE_EL2_REGS. 360CTX_INCLUDE_EL2_REGS := 0 361 362# Select workaround for AT speculative behaviour. 363ERRATA_SPECULATIVE_AT := 0 364 365# Trap RAS error record access from Non secure 366RAS_TRAP_NS_ERR_REC_ACCESS := 0 367 368# Build option to create cot descriptors using fconf 369COT_DESC_IN_DTB := 0 370 371# Build option to provide OpenSSL directory path 372OPENSSL_DIR := /usr 373 374# Select the openssl binary provided in OPENSSL_DIR variable 375ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 376 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 377else 378 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 379endif 380 381# Build option to use the SP804 timer instead of the generic one 382USE_SP804_TIMER := 0 383 384# Build option to define number of firmware banks, used in firmware update 385# metadata structure. 386NR_OF_FW_BANKS := 2 387 388# Build option to define number of images in firmware bank, used in firmware 389# update metadata structure. 390NR_OF_IMAGES_IN_FW_BANK := 1 391 392# Disable Firmware update support by default 393PSA_FWU_SUPPORT := 0 394 395# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 396# is enabled. 397ifeq ($(PSA_FWU_SUPPORT),1) 398PSA_FWU_METADATA_FW_STORE_DESC := 1 399else 400PSA_FWU_METADATA_FW_STORE_DESC := 0 401endif 402 403# Dynamic Root of Trust for Measurement support 404DRTM_SUPPORT := 0 405 406# Check platform if cache management operations should be performed. 407# Disabled by default. 408CONDITIONAL_CMO := 0 409 410# By default, disable SPMD Logical partitions 411ENABLE_SPMD_LP := 0 412 413# By default, disable PSA crypto (use MbedTLS legacy crypto API). 414PSA_CRYPTO := 0 415 416# getc() support from the console(s). 417# Disabled by default because it constitutes an attack vector into TF-A. It 418# should only be enabled if there is a use case for it. 419ENABLE_CONSOLE_GETC := 0 420 421# Build option to disable EL2 when it is not used. 422# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 423# functions must be enabled by platforms if they require it. 424# Disabled by default. 425INIT_UNUSED_NS_EL2 := 0 426 427# Disable including MPAM EL2 registers in context by default since currently 428# it's only enabled for NS world 429CTX_INCLUDE_MPAM_REGS := 0 430 431# Enable context memory usage reporting during BL31 setup. 432PLATFORM_REPORT_CTX_MEM_USE := 0 433 434# Request a custom addition to the BL31 linker script 435PLAT_EXTRA_LD_SCRIPT := 0 436 437# Enable early console 438EARLY_CONSOLE := 0 439 440# Allow platforms to save/restore DSU PMU registers over a power cycle. 441# Disabled by default and must be enabled by individual platforms. 442PRESERVE_DSU_PMU_REGS := 0 443 444# Flag to enable an RME payload 445ENABLE_RMM := 0 446 447# Enable RMMD to forward attestation requests from RMM to EL3. 448RMMD_ENABLE_EL3_TOKEN_SIGN := 0 449 450# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP). 451# This flag is temporary and it is expected once the interface is 452# finalized, this flag will be removed. 453RMMD_ENABLE_IDE_KEY_PROG := 0 454 455# Enable RMM v1.x compatibility mode 456RMM_V1_COMPAT := 0 457 458# Live firmware activation support 459LFA_SUPPORT := 0 460 461# Enable support for arm DSU driver. 462USE_DSU_DRIVER := 0 463 464# Define the separation of BL2 flag, by default it is disabled. 465SEPARATE_BL2_FIP := 0 466 467# Disable NUMA awareness for per-CPU framework by default. Platforms should 468# enable this feature by setting PLATFORM_NODE_COUNT > 1 469PLATFORM_NODE_COUNT := 1 470 471# Support for live activation of SPs managed by S-EL2 SPMC 472SUPPORT_SP_LIVE_ACTIVATION := 0 473 474# Negative I/O test: intentionally report a short read for a selected 475# image_id. Test/CI only. Do not enable in production builds. 476TEST_IO_SHORT_READ_FI := 0 477TEST_IO_SHORT_READ_FI_IMAGE_ID := 0 478 479# Enable the FIRME interface. 480FIRME_SUPPORT := 0 481 482# Flag to enable the spinlock implementation variant using the FEAT_LSE 483# compare-and-swap instruction. 484USE_SPINLOCK_CAS ?= 0 485 486#---- 487# 8.1 488#---- 489 490# Flag to enable access to Privileged Access Never bit of PSTATE. 491ENABLE_FEAT_PAN ?= 0 492 493# Flag to enable Virtualization Host Extensions. 494ENABLE_FEAT_VHE ?= 0 495 496#---- 497# 8.2 498#---- 499 500# Enable RAS Support. 501ENABLE_FEAT_RAS ?= 0 502 503#---- 504# 8.3 505#---- 506 507# Flag to enable Pointer Authentication. Internal flag not meant for 508# direct setting. Use BRANCH_PROTECTION to enable PAUTH. 509ENABLE_PAUTH ?= 0 510 511# FEAT_PAUTH_LR is an optional architectural feature, so this flag must be set 512# manually in addition to the BRANCH_PROTECTION flag which is used for other 513# branch protection and pointer authentication features. 514ENABLE_FEAT_PAUTH_LR ?= 0 515 516# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 517# must be set to 1 if the platform wants to use this feature in the Secure 518# world. It is not necessary for use in the Non-secure world. 519CTX_INCLUDE_PAUTH_REGS ?= 0 520 521 522#---- 523# 8.4 524#---- 525 526# Flag to enable Secure EL-2 feature. 527ENABLE_FEAT_SEL2 ?= 0 528 529# By default, disable trace filter control register access to lower non-secure 530# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but 531# trace filter control register access is unused if FEAT_TRF is implemented. 532ENABLE_TRF_FOR_NS ?= 0 533 534# Flag to enable Data Independent Timing instructions. 535ENABLE_FEAT_DIT ?= 0 536 537#---- 538# 8.5 539#---- 540 541# Flag to enable Branch Target Identification. 542# Internal flag not meant for direct setting. 543# Use BRANCH_PROTECTION to enable BTI. 544ENABLE_BTI ?= 0 545 546# Flag to enable access to the Random Number Generator registers. 547ENABLE_FEAT_RNG ?= 0 548 549# Flag to enable Speculation Barrier Instruction. 550ENABLE_FEAT_SB ?= 0 551 552#---- 553# 8.6 554#---- 555 556# Flag to enable access to the CNTPOFF_EL2 register. 557ENABLE_FEAT_ECV ?= 0 558 559# Flag to enable access to the HDFGRTR_EL2 register. 560ENABLE_FEAT_FGT ?= 0 561 562#---- 563# 8.7 564#---- 565 566# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 567ENABLE_FEAT_HCX ?= 0 568 569#---- 570# 8.8 571#---- 572 573# Flag to enable FEAT_MOPS (Standardization of Memory operations) 574# when INIT_UNUSED_NS_EL2 = 1 575ENABLE_FEAT_MOPS ?= 0 576 577#---- 578# 8.9 579#---- 580 581# Flag to enable access to TCR2 (FEAT_TCR2). 582ENABLE_FEAT_TCR2 ?= 0 583 584# Flag to enable access to SCTLR2 (FEAT_SCTLR2). 585ENABLE_FEAT_SCTLR2 ?= 0 586 587# 588################################################################################ 589# Optional Features defaulted to 0 or 2, if they are not enabled from 590# build option. Can also be disabled or enabled by platform if needed. 591################################################################################ 592# 593 594#---- 595# 8.0 596#---- 597 598# Flag to enable support for clrbhb instruction. 599ENABLE_FEAT_CLRBHB ?= 0 600 601# Flag to enable CSV2_2 extension. 602ENABLE_FEAT_CSV2_2 ?= 0 603 604# Flag to enable CSV2_3 extension. FEAT_CSV2_3 enables access to the 605# SCXTNUM_ELx register. 606ENABLE_FEAT_CSV2_3 ?= 0 607 608# By default, disable access of trace system registers from NS lower 609# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 610# system register trace is implemented. This feature is available if 611# trace unit such as ETMv4.x, This feature is OPTIONAL and is only 612# permitted in Armv8 implementations. 613ENABLE_SYS_REG_TRACE_FOR_NS ?= 0 614 615#---- 616# 8.2 617#---- 618 619# Build option to enable/disable the Statistical Profiling Extension, 620# keep it enabled by default for AArch64. 621ifeq (${ARCH},aarch64) 622 ENABLE_SPE_FOR_NS ?= 2 623else ifeq (${ARCH},aarch32) 624 ENABLE_SPE_FOR_NS := 0 625endif 626 627# Enable SVE for non-secure world by default. 628ifeq (${ARCH},aarch64) 629 ENABLE_SVE_FOR_NS ?= 2 630# SVE is only supported on AArch64 so disable it on AArch32. 631else ifeq (${ARCH},aarch32) 632 ENABLE_SVE_FOR_NS := 0 633endif 634 635#---- 636# 8.4 637#---- 638 639# Feature flags for supporting Activity monitor extensions. 640ENABLE_FEAT_AMU ?= 0 641ENABLE_AMU_AUXILIARY_COUNTERS ?= 0 642AMU_RESTRICT_COUNTERS ?= 1 643 644# Build option to enable MPAM for lower ELs. 645# Enabling it by default 646ifeq (${ARCH},aarch64) 647 ENABLE_FEAT_MPAM ?= 2 648else ifeq (${ARCH},aarch32) 649 ENABLE_FEAT_MPAM := 0 650endif 651 652# Include nested virtualization control (Armv8.4-NV) registers in cpu context. 653# This must be set to 1 if architecture implements Nested Virtualization 654# Extension and platform wants to use this feature in the Secure world. 655CTX_INCLUDE_NEVE_REGS ?= 0 656 657#---- 658# 8.5 659#---- 660 661# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS 662# registers, by setting SCR_EL3.TRNDR. 663ENABLE_FEAT_RNG_TRAP ?= 0 664 665# Enable FEAT_MTE2. This must be set to 1 if the platform wants 666# to use this feature and is enabled at ELX. 667ENABLE_FEAT_MTE2 ?= 0 668 669#---- 670# 8.6 671#---- 672 673# Flag to enable AMUv1p1 extension. 674ENABLE_FEAT_AMUv1p1 ?= 0 675 676# Flag to enable delayed trapping of WFE instruction (FEAT_TWED). 677ENABLE_FEAT_TWED ?= 0 678 679# In v8.6+ platforms with delayed trapping of WFE being supported 680# via FEAT_TWED, this flag takes the delay value to be set in the 681# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented. 682# By default it takes 0, and need to be updated by the platforms. 683TWED_DELAY ?= 0 684 685# Disable MTPMU if FEAT_MTPMU is supported. 686DISABLE_MTPMU ?= 0 687 688# Flag to enable FEAT_FGT2 (Fine Granular Traps 2) 689ENABLE_FEAT_FGT2 ?= 0 690 691# LoadStore64Bytes extension using the ACCDATA_EL1 system register 692ENABLE_FEAT_LS64_ACCDATA ?= 0 693 694#---- 695# 8.8 696#---- 697 698# Flag to enable FEAT_THE (Translation Hardening Extension) 699ENABLE_FEAT_THE ?= 0 700 701#---- 702# 8.9 703#---- 704 705# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE). 706ENABLE_FEAT_S2PIE ?= 0 707 708# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE). 709ENABLE_FEAT_S1PIE ?= 0 710 711# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE). 712ENABLE_FEAT_S2POE ?= 0 713 714# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE). 715ENABLE_FEAT_S1POE ?= 0 716 717# Flag to enable access to Arm v8.9 Debug extension 718ENABLE_FEAT_DEBUGV8P9 ?= 0 719 720# AIE extension using the (A)MAIR2 system registers 721ENABLE_FEAT_AIE ?= 0 722 723# PFAR extension using the PFAR system registers 724ENABLE_FEAT_PFAR ?= 0 725 726#------------------------------------------------------------- 727# Non-standard feature 728#------------------------------------------------------------- 729ENABLE_FEAT_MORELLO ?= 0 730 731#---- 732# 9.0 733#---- 734 735# Scalable Matrix Extension for non-secure world. 736ENABLE_SME_FOR_NS ?= 0 737 738# Scalable Vector Extension for secure world. 739ENABLE_SVE_FOR_SWD ?= 0 740 741# By default, disable access of trace buffer control registers from NS 742# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 743# if FEAT_TRBE is implemented. 744# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 745# AArch32. 746ifeq (${ARCH},aarch64) 747 ENABLE_TRBE_FOR_NS ?= 0 748else ifeq (${ARCH},aarch32) 749 ifneq ($(or $(ENABLE_TRBE_FOR_NS),0),0) 750 $(error ENABLE_TRBE_FOR_NS is not supported for AArch32) 751 else 752 ENABLE_TRBE_FOR_NS := 0 753 endif 754endif 755 756# Flag that enables hardware injection of undefined exceptions 757ENABLE_FEAT_UINJ ?= 0 758 759#---- 760# 9.2 761#---- 762 763# Flag to enable Realm Management Extension (FEAT_RME). 764ENABLE_FEAT_RME ?= 0 765 766# Scalable Matrix Extension version 2 for non-secure world. 767ENABLE_SME2_FOR_NS ?= 0 768 769# Scalable Matrix Extension for secure world. 770ENABLE_SME_FOR_SWD ?= 0 771 772# By default, disable access to branch record buffer control registers from NS 773# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 774# if FEAT_BRBE is implemented. 775ENABLE_BRBE_FOR_NS ?= 0 776 777# Flag to enable Floating point exception Mode Register Feature (FEAT_FPMR) 778ENABLE_FEAT_FPMR ?= 0 779 780# Flag to enable Memory Encryption Contexts (FEAT_MEC). 781ENABLE_FEAT_MEC ?= 0 782 783#---- 784# 9.3 785#---- 786# Flag to enable access to Arm v9.3 FEAT_D128 extension 787ENABLE_FEAT_D128 ?= 0 788 789# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE) 790ENABLE_FEAT_GCIE ?= 0 791 792# Enables access to PE-side MPAM bandwidth controls (FEAT_MPAM_PE_BW_CTRL) 793ENABLE_FEAT_MPAM_PE_BW_CTRL ?= 0 794 795# Flag to enable Exception-based Event Profiling (FEAT_EBEP) 796ENABLE_FEAT_EBEP ?= 0 797 798#---- 799#9.4 800#---- 801 802# Flag to enable FEAT_RME_GDI 803ENABLE_FEAT_RME_GDI ?= 0 804 805# Flag to enable access to Guarded Control Stack (FEAT_GCS). 806ENABLE_FEAT_GCS ?= 0 807 808# Flag to enable Fine Grained Write Traps (FEAT_FGWTE3) for EL3. 809ENABLE_FEAT_FGWTE3 ?= 0 810 811# Flag to enable checked pointer arithmetic (FEAT_CPA2) for EL3. 812# We don't have a flag for FEAT_CPA since that has no effect on software 813ENABLE_FEAT_CPA2 ?= 0 814 815# Flag to enable Enhanced Software Step Extension (FEAT_STEP2) 816ENABLE_FEAT_STEP2 ?= 0 817 818# Flag to enable Hardware Dirty state tracking structure (FEAT_HDBSS). 819ENABLE_FEAT_HDBSS ?= 0 820 821# Flag to enable Hardening Address and Context Debug Banked State (FEAT_HACDBS). 822ENABLE_FEAT_HACDBS ?= 0 823 824#---- 825#9.6 826#---- 827 828# Flag to enable trapping of ID registers to EL3 829ENABLE_FEAT_IDTE3 ?= 0 830