1# 2# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# By default, consider that the platform may release several CPUs out of reset. 31# The platform Makefile is free to override this value. 32COLD_BOOT_SINGLE_CPU := 0 33 34# For Chain of Trust 35CREATE_KEYS := 1 36 37# Build flag to include AArch32 registers in cpu context save and restore during 38# world switch. This flag must be set to 0 for AArch64-only platforms. 39CTX_INCLUDE_AARCH32_REGS := 1 40 41# Include FP registers in cpu context 42CTX_INCLUDE_FPREGS := 0 43 44# Debug build 45DEBUG := 0 46 47# Build platform 48DEFAULT_PLAT := fvp 49 50# Flag to enable Performance Measurement Framework 51ENABLE_PMF := 0 52 53# Flag to enable PSCI STATs functionality 54ENABLE_PSCI_STAT := 0 55 56# Flag to enable runtime instrumentation using PMF 57ENABLE_RUNTIME_INSTRUMENTATION := 0 58 59# Flag to enable stack corruption protection 60ENABLE_STACK_PROTECTOR := 0 61 62# Flag to enable exception handling in EL3 63EL3_EXCEPTION_HANDLING := 0 64 65# Build flag to treat usage of deprecated platform and framework APIs as error. 66ERROR_DEPRECATED := 0 67 68# Byte alignment that each component in FIP is aligned to 69FIP_ALIGN := 0 70 71# Default FIP file name 72FIP_NAME := fip.bin 73 74# Default FWU_FIP file name 75FWU_FIP_NAME := fwu_fip.bin 76 77# For Chain of Trust 78GENERATE_COT := 0 79 80# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 81# default, they are for Secure EL1. 82GICV2_G0_FOR_EL3 := 0 83 84# Whether system coherency is managed in hardware, without explicit software 85# operations. 86HW_ASSISTED_COHERENCY := 0 87 88# Set the default algorithm for the generation of Trusted Board Boot keys 89KEY_ALG := rsa 90 91# Flag to enable new version of image loading 92LOAD_IMAGE_V2 := 0 93 94# Use the new console API that allows registering more than one console instance 95# at once. Use = instead of := to dynamically default to ERROR_DEPRECATED. 96MULTI_CONSOLE_API = $(ERROR_DEPRECATED) 97 98# NS timer register save and restore 99NS_TIMER_SWITCH := 0 100 101# Build PL011 UART driver in minimal generic UART mode 102PL011_GENERIC_UART := 0 103 104# By default, consider that the platform's reset address is not programmable. 105# The platform Makefile is free to override this value. 106PROGRAMMABLE_RESET_ADDRESS := 0 107 108# Flag used to choose the power state format viz Extended State-ID or the 109# Original format. 110PSCI_EXTENDED_STATE_ID := 0 111 112# By default, BL1 acts as the reset handler, not BL31 113RESET_TO_BL31 := 0 114 115# For Chain of Trust 116SAVE_KEYS := 0 117 118# Software Delegated Exception support 119SDEI_SUPPORT := 0 120 121# Whether code and read-only data should be put on separate memory pages. The 122# platform Makefile is free to override this value. 123SEPARATE_CODE_AND_RODATA := 0 124 125# SPD choice 126SPD := none 127 128# For including the Secure Partition Manager 129ENABLE_SPM := 0 130 131# Flag to introduce an infinite loop in BL1 just before it exits into the next 132# image. This is meant to help debugging the post-BL2 phase. 133SPIN_ON_BL1_EXIT := 0 134 135# Flags to build TF with Trusted Boot support 136TRUSTED_BOARD_BOOT := 0 137 138# Build option to choose whether Trusted firmware uses Coherent memory or not. 139USE_COHERENT_MEM := 1 140 141# Use tbbr_oid.h instead of platform_oid.h 142USE_TBBR_DEFS = $(ERROR_DEPRECATED) 143 144# Build verbosity 145V := 0 146 147# Whether to enable D-Cache early during warm boot. This is usually 148# applicable for platforms wherein interconnect programming is not 149# required to enable cache coherency after warm reset (eg: single cluster 150# platforms). 151WARMBOOT_ENABLE_DCACHE_EARLY := 0 152 153# Build option to enable/disable the Statistical Profiling Extensions 154ENABLE_SPE_FOR_LOWER_ELS := 1 155 156# SPE is only supported on AArch64 so disable it on AArch32. 157ifeq (${ARCH},aarch32) 158 override ENABLE_SPE_FOR_LOWER_ELS := 0 159endif 160 161ENABLE_AMU := 0 162 163# By default, enable Scalable Vector Extension if implemented for Non-secure 164# lower ELs 165# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 166ifneq (${ARCH},aarch32) 167 ENABLE_SVE_FOR_NS := 1 168else 169 override ENABLE_SVE_FOR_NS := 0 170endif 171