1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# Execute BL2 at EL3 31BL2_AT_EL3 := 0 32 33# BL2 image is stored in XIP memory, for now, this option is only supported 34# when BL2_AT_EL3 is 1. 35BL2_IN_XIP_MEM := 0 36 37# By default, consider that the platform may release several CPUs out of reset. 38# The platform Makefile is free to override this value. 39COLD_BOOT_SINGLE_CPU := 0 40 41# Flag to compile in coreboot support code. Exclude by default. The coreboot 42# Makefile system will set this when compiling TF as part of a coreboot image. 43COREBOOT := 0 44 45# For Chain of Trust 46CREATE_KEYS := 1 47 48# Build flag to include AArch32 registers in cpu context save and restore during 49# world switch. This flag must be set to 0 for AArch64-only platforms. 50CTX_INCLUDE_AARCH32_REGS := 1 51 52# Include FP registers in cpu context 53CTX_INCLUDE_FPREGS := 0 54 55# Debug build 56DEBUG := 0 57 58# Build platform 59DEFAULT_PLAT := fvp 60 61# Flag to enable Performance Measurement Framework 62ENABLE_PMF := 0 63 64# Flag to enable PSCI STATs functionality 65ENABLE_PSCI_STAT := 0 66 67# Flag to enable runtime instrumentation using PMF 68ENABLE_RUNTIME_INSTRUMENTATION := 0 69 70# Flag to enable stack corruption protection 71ENABLE_STACK_PROTECTOR := 0 72 73# Flag to enable exception handling in EL3 74EL3_EXCEPTION_HANDLING := 0 75 76# Build flag to treat usage of deprecated platform and framework APIs as error. 77ERROR_DEPRECATED := 0 78 79# Byte alignment that each component in FIP is aligned to 80FIP_ALIGN := 0 81 82# Default FIP file name 83FIP_NAME := fip.bin 84 85# Default FWU_FIP file name 86FWU_FIP_NAME := fwu_fip.bin 87 88# For Chain of Trust 89GENERATE_COT := 0 90 91# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 92# default, they are for Secure EL1. 93GICV2_G0_FOR_EL3 := 0 94 95# Route External Aborts to EL3. Disabled by default; External Aborts are handled 96# by lower ELs. 97HANDLE_EA_EL3_FIRST := 0 98 99# Whether system coherency is managed in hardware, without explicit software 100# operations. 101HW_ASSISTED_COHERENCY := 0 102 103# Set the default algorithm for the generation of Trusted Board Boot keys 104KEY_ALG := rsa 105 106# Flag to enable new version of image loading 107LOAD_IMAGE_V2 := 0 108 109# Enable use of the console API allowing multiple consoles to be registered 110# at the same time. 111MULTI_CONSOLE_API := 0 112 113# NS timer register save and restore 114NS_TIMER_SWITCH := 0 115 116# Build PL011 UART driver in minimal generic UART mode 117PL011_GENERIC_UART := 0 118 119# By default, consider that the platform's reset address is not programmable. 120# The platform Makefile is free to override this value. 121PROGRAMMABLE_RESET_ADDRESS := 0 122 123# Flag used to choose the power state format viz Extended State-ID or the 124# Original format. 125PSCI_EXTENDED_STATE_ID := 0 126 127# Enable RAS support 128RAS_EXTENSION := 0 129 130# By default, BL1 acts as the reset handler, not BL31 131RESET_TO_BL31 := 0 132 133# For Chain of Trust 134SAVE_KEYS := 0 135 136# Software Delegated Exception support 137SDEI_SUPPORT := 0 138 139# Whether code and read-only data should be put on separate memory pages. The 140# platform Makefile is free to override this value. 141SEPARATE_CODE_AND_RODATA := 0 142 143# Default to SMCCC Version 1.X 144SMCCC_MAJOR_VERSION := 1 145 146# SPD choice 147SPD := none 148 149# For including the Secure Partition Manager 150ENABLE_SPM := 0 151 152# Flag to introduce an infinite loop in BL1 just before it exits into the next 153# image. This is meant to help debugging the post-BL2 phase. 154SPIN_ON_BL1_EXIT := 0 155 156# Flags to build TF with Trusted Boot support 157TRUSTED_BOARD_BOOT := 0 158 159# Build option to choose whether Trusted firmware uses Coherent memory or not. 160USE_COHERENT_MEM := 1 161 162# Use tbbr_oid.h instead of platform_oid.h 163USE_TBBR_DEFS = $(ERROR_DEPRECATED) 164 165# Build verbosity 166V := 0 167 168# Whether to enable D-Cache early during warm boot. This is usually 169# applicable for platforms wherein interconnect programming is not 170# required to enable cache coherency after warm reset (eg: single cluster 171# platforms). 172WARMBOOT_ENABLE_DCACHE_EARLY := 0 173 174# Build option to enable/disable the Statistical Profiling Extensions 175ENABLE_SPE_FOR_LOWER_ELS := 1 176 177# SPE is only supported on AArch64 so disable it on AArch32. 178ifeq (${ARCH},aarch32) 179 override ENABLE_SPE_FOR_LOWER_ELS := 0 180endif 181 182ENABLE_AMU := 0 183 184# By default, enable Scalable Vector Extension if implemented for Non-secure 185# lower ELs 186# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 187ifneq (${ARCH},aarch32) 188 ENABLE_SVE_FOR_NS := 1 189else 190 override ENABLE_SVE_FOR_NS := 0 191endif 192