1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# Execute BL2 at EL3 31BL2_AT_EL3 := 0 32 33# By default, consider that the platform may release several CPUs out of reset. 34# The platform Makefile is free to override this value. 35COLD_BOOT_SINGLE_CPU := 0 36 37# Flag to compile in coreboot support code. Exclude by default. The coreboot 38# Makefile system will set this when compiling TF as part of a coreboot image. 39COREBOOT := 0 40 41# For Chain of Trust 42CREATE_KEYS := 1 43 44# Build flag to include AArch32 registers in cpu context save and restore during 45# world switch. This flag must be set to 0 for AArch64-only platforms. 46CTX_INCLUDE_AARCH32_REGS := 1 47 48# Include FP registers in cpu context 49CTX_INCLUDE_FPREGS := 0 50 51# Debug build 52DEBUG := 0 53 54# Build platform 55DEFAULT_PLAT := fvp 56 57# Flag to enable Performance Measurement Framework 58ENABLE_PMF := 0 59 60# Flag to enable PSCI STATs functionality 61ENABLE_PSCI_STAT := 0 62 63# Flag to enable runtime instrumentation using PMF 64ENABLE_RUNTIME_INSTRUMENTATION := 0 65 66# Flag to enable stack corruption protection 67ENABLE_STACK_PROTECTOR := 0 68 69# Flag to enable exception handling in EL3 70EL3_EXCEPTION_HANDLING := 0 71 72# Build flag to treat usage of deprecated platform and framework APIs as error. 73ERROR_DEPRECATED := 0 74 75# Byte alignment that each component in FIP is aligned to 76FIP_ALIGN := 0 77 78# Default FIP file name 79FIP_NAME := fip.bin 80 81# Default FWU_FIP file name 82FWU_FIP_NAME := fwu_fip.bin 83 84# For Chain of Trust 85GENERATE_COT := 0 86 87# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 88# default, they are for Secure EL1. 89GICV2_G0_FOR_EL3 := 0 90 91# Whether system coherency is managed in hardware, without explicit software 92# operations. 93HW_ASSISTED_COHERENCY := 0 94 95# Set the default algorithm for the generation of Trusted Board Boot keys 96KEY_ALG := rsa 97 98# Flag to enable new version of image loading 99LOAD_IMAGE_V2 := 0 100 101# Enable use of the console API allowing multiple consoles to be registered 102# at the same time. 103MULTI_CONSOLE_API := 0 104 105# NS timer register save and restore 106NS_TIMER_SWITCH := 0 107 108# Build PL011 UART driver in minimal generic UART mode 109PL011_GENERIC_UART := 0 110 111# By default, consider that the platform's reset address is not programmable. 112# The platform Makefile is free to override this value. 113PROGRAMMABLE_RESET_ADDRESS := 0 114 115# Flag used to choose the power state format viz Extended State-ID or the 116# Original format. 117PSCI_EXTENDED_STATE_ID := 0 118 119# By default, BL1 acts as the reset handler, not BL31 120RESET_TO_BL31 := 0 121 122# For Chain of Trust 123SAVE_KEYS := 0 124 125# Software Delegated Exception support 126SDEI_SUPPORT := 0 127 128# Whether code and read-only data should be put on separate memory pages. The 129# platform Makefile is free to override this value. 130SEPARATE_CODE_AND_RODATA := 0 131 132# SPD choice 133SPD := none 134 135# For including the Secure Partition Manager 136ENABLE_SPM := 0 137 138# Flag to introduce an infinite loop in BL1 just before it exits into the next 139# image. This is meant to help debugging the post-BL2 phase. 140SPIN_ON_BL1_EXIT := 0 141 142# Flags to build TF with Trusted Boot support 143TRUSTED_BOARD_BOOT := 0 144 145# Build option to choose whether Trusted firmware uses Coherent memory or not. 146USE_COHERENT_MEM := 1 147 148# Use tbbr_oid.h instead of platform_oid.h 149USE_TBBR_DEFS = $(ERROR_DEPRECATED) 150 151# Build verbosity 152V := 0 153 154# Whether to enable D-Cache early during warm boot. This is usually 155# applicable for platforms wherein interconnect programming is not 156# required to enable cache coherency after warm reset (eg: single cluster 157# platforms). 158WARMBOOT_ENABLE_DCACHE_EARLY := 0 159 160# Build option to enable/disable the Statistical Profiling Extensions 161ENABLE_SPE_FOR_LOWER_ELS := 1 162 163# SPE is only supported on AArch64 so disable it on AArch32. 164ifeq (${ARCH},aarch32) 165 override ENABLE_SPE_FOR_LOWER_ELS := 0 166endif 167 168ENABLE_AMU := 0 169 170# By default, enable Scalable Vector Extension if implemented for Non-secure 171# lower ELs 172# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 173ifneq (${ARCH},aarch32) 174 ENABLE_SVE_FOR_NS := 1 175else 176 override ENABLE_SVE_FOR_NS := 0 177endif 178