12fae4b1eSJeenu Viswambharan# 2c877b414SJeenu Viswambharan# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 32fae4b1eSJeenu Viswambharan# 42fae4b1eSJeenu Viswambharan# Redistribution and use in source and binary forms, with or without 52fae4b1eSJeenu Viswambharan# modification, are permitted provided that the following conditions are met: 62fae4b1eSJeenu Viswambharan# 72fae4b1eSJeenu Viswambharan# Redistributions of source code must retain the above copyright notice, this 82fae4b1eSJeenu Viswambharan# list of conditions and the following disclaimer. 92fae4b1eSJeenu Viswambharan# 102fae4b1eSJeenu Viswambharan# Redistributions in binary form must reproduce the above copyright notice, 112fae4b1eSJeenu Viswambharan# this list of conditions and the following disclaimer in the documentation 122fae4b1eSJeenu Viswambharan# and/or other materials provided with the distribution. 132fae4b1eSJeenu Viswambharan# 142fae4b1eSJeenu Viswambharan# Neither the name of ARM nor the names of its contributors may be used 152fae4b1eSJeenu Viswambharan# to endorse or promote products derived from this software without specific 162fae4b1eSJeenu Viswambharan# prior written permission. 172fae4b1eSJeenu Viswambharan# 182fae4b1eSJeenu Viswambharan# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 192fae4b1eSJeenu Viswambharan# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 202fae4b1eSJeenu Viswambharan# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 212fae4b1eSJeenu Viswambharan# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 222fae4b1eSJeenu Viswambharan# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 232fae4b1eSJeenu Viswambharan# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 242fae4b1eSJeenu Viswambharan# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 252fae4b1eSJeenu Viswambharan# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 262fae4b1eSJeenu Viswambharan# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 272fae4b1eSJeenu Viswambharan# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 282fae4b1eSJeenu Viswambharan# POSSIBILITY OF SUCH DAMAGE. 292fae4b1eSJeenu Viswambharan# 302fae4b1eSJeenu Viswambharan 312fae4b1eSJeenu Viswambharan# Default, static values for build variables, listed in alphabetic order. 322fae4b1eSJeenu Viswambharan# Dependencies between build options, if any, are handled in the top-level 332fae4b1eSJeenu Viswambharan# Makefile, after this file is included. This ensures that the former is better 342fae4b1eSJeenu Viswambharan# poised to handle dependencies, as all build variables would have a default 352fae4b1eSJeenu Viswambharan# value by then. 362fae4b1eSJeenu Viswambharan 372fae4b1eSJeenu Viswambharan# The AArch32 Secure Payload to be built as BL32 image 382fae4b1eSJeenu ViswambharanAARCH32_SP := none 392fae4b1eSJeenu Viswambharan 402fae4b1eSJeenu Viswambharan# The Target build architecture. Supported values are: aarch64, aarch32. 412fae4b1eSJeenu ViswambharanARCH := aarch64 422fae4b1eSJeenu Viswambharan 432fae4b1eSJeenu Viswambharan# Determine the version of ARM CCI product used in the platform. The platform 442fae4b1eSJeenu Viswambharan# port can change this value if needed. 452fae4b1eSJeenu ViswambharanARM_CCI_PRODUCT_ID := 400 462fae4b1eSJeenu Viswambharan 47c877b414SJeenu Viswambharan# ARM Architecture major and minor versions: 8.0 by default. 48c877b414SJeenu ViswambharanARM_ARCH_MAJOR := 8 49c877b414SJeenu ViswambharanARM_ARCH_MINOR := 0 50c877b414SJeenu Viswambharan 512fae4b1eSJeenu Viswambharan# Determine the version of ARM GIC architecture to use for interrupt management 522fae4b1eSJeenu Viswambharan# in EL3. The platform port can change this value if needed. 532fae4b1eSJeenu ViswambharanARM_GIC_ARCH := 2 542fae4b1eSJeenu Viswambharan 552fae4b1eSJeenu Viswambharan# Flag used to indicate if ASM_ASSERTION should be enabled for the build. 562fae4b1eSJeenu ViswambharanASM_ASSERTION := 0 572fae4b1eSJeenu Viswambharan 582fae4b1eSJeenu Viswambharan# Base commit to perform code check on 592fae4b1eSJeenu ViswambharanBASE_COMMIT := origin/master 602fae4b1eSJeenu Viswambharan 612fae4b1eSJeenu Viswambharan# By default, consider that the platform may release several CPUs out of reset. 622fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 632fae4b1eSJeenu ViswambharanCOLD_BOOT_SINGLE_CPU := 0 642fae4b1eSJeenu Viswambharan 652fae4b1eSJeenu Viswambharan# For Chain of Trust 662fae4b1eSJeenu ViswambharanCREATE_KEYS := 1 672fae4b1eSJeenu Viswambharan 682fae4b1eSJeenu Viswambharan# Build flag to include AArch32 registers in cpu context save and restore during 692fae4b1eSJeenu Viswambharan# world switch. This flag must be set to 0 for AArch64-only platforms. 702fae4b1eSJeenu ViswambharanCTX_INCLUDE_AARCH32_REGS := 1 712fae4b1eSJeenu Viswambharan 722fae4b1eSJeenu Viswambharan# Include FP registers in cpu context 732fae4b1eSJeenu ViswambharanCTX_INCLUDE_FPREGS := 0 742fae4b1eSJeenu Viswambharan 752fae4b1eSJeenu Viswambharan# Debug build 762fae4b1eSJeenu ViswambharanDEBUG := 0 772fae4b1eSJeenu Viswambharan 782fae4b1eSJeenu Viswambharan# Build platform 792fae4b1eSJeenu ViswambharanDEFAULT_PLAT := fvp 802fae4b1eSJeenu Viswambharan 812fae4b1eSJeenu Viswambharan# By default, use the -pedantic option in the gcc command line 822fae4b1eSJeenu ViswambharanDISABLE_PEDANTIC := 0 832fae4b1eSJeenu Viswambharan 842fae4b1eSJeenu Viswambharan# Flag to enable Performance Measurement Framework 852fae4b1eSJeenu ViswambharanENABLE_PMF := 0 862fae4b1eSJeenu Viswambharan 872fae4b1eSJeenu Viswambharan# Flag to enable PSCI STATs functionality 882fae4b1eSJeenu ViswambharanENABLE_PSCI_STAT := 0 892fae4b1eSJeenu Viswambharan 902fae4b1eSJeenu Viswambharan# Flag to enable runtime instrumentation using PMF 912fae4b1eSJeenu ViswambharanENABLE_RUNTIME_INSTRUMENTATION := 0 922fae4b1eSJeenu Viswambharan 9351faada7SDouglas Raillard# Flag to enable stack corruption protection 9451faada7SDouglas RaillardENABLE_STACK_PROTECTOR := 0 9551faada7SDouglas Raillard 962fae4b1eSJeenu Viswambharan# Build flag to treat usage of deprecated platform and framework APIs as error. 972fae4b1eSJeenu ViswambharanERROR_DEPRECATED := 0 982fae4b1eSJeenu Viswambharan 991c75d5dfSMasahiro Yamada# Byte alignment that each component in FIP is aligned to 1001c75d5dfSMasahiro YamadaFIP_ALIGN := 0 1011c75d5dfSMasahiro Yamada 1022fae4b1eSJeenu Viswambharan# Default FIP file name 1032fae4b1eSJeenu ViswambharanFIP_NAME := fip.bin 1042fae4b1eSJeenu Viswambharan 1052fae4b1eSJeenu Viswambharan# Default FWU_FIP file name 1062fae4b1eSJeenu ViswambharanFWU_FIP_NAME := fwu_fip.bin 1072fae4b1eSJeenu Viswambharan 1082fae4b1eSJeenu Viswambharan# For Chain of Trust 1092fae4b1eSJeenu ViswambharanGENERATE_COT := 0 1102fae4b1eSJeenu Viswambharan 1113c251af3SJeenu Viswambharan# Whether system coherency is managed in hardware, without explicit software 1123c251af3SJeenu Viswambharan# operations. 1133c251af3SJeenu ViswambharanHW_ASSISTED_COHERENCY := 0 1143c251af3SJeenu Viswambharan 1152fae4b1eSJeenu Viswambharan# Flag to enable new version of image loading 1162fae4b1eSJeenu ViswambharanLOAD_IMAGE_V2 := 0 1172fae4b1eSJeenu Viswambharan 1182fae4b1eSJeenu Viswambharan# NS timer register save and restore 1192fae4b1eSJeenu ViswambharanNS_TIMER_SWITCH := 0 1202fae4b1eSJeenu Viswambharan 1212fae4b1eSJeenu Viswambharan# Build PL011 UART driver in minimal generic UART mode 1222fae4b1eSJeenu ViswambharanPL011_GENERIC_UART := 0 1232fae4b1eSJeenu Viswambharan 1242fae4b1eSJeenu Viswambharan# By default, consider that the platform's reset address is not programmable. 1252fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 1262fae4b1eSJeenu ViswambharanPROGRAMMABLE_RESET_ADDRESS := 0 1272fae4b1eSJeenu Viswambharan 1282fae4b1eSJeenu Viswambharan# Flag used to choose the power state format viz Extended State-ID or the 1292fae4b1eSJeenu Viswambharan# Original format. 1302fae4b1eSJeenu ViswambharanPSCI_EXTENDED_STATE_ID := 0 1312fae4b1eSJeenu Viswambharan 1322fae4b1eSJeenu Viswambharan# By default, BL1 acts as the reset handler, not BL31 1332fae4b1eSJeenu ViswambharanRESET_TO_BL31 := 0 1342fae4b1eSJeenu Viswambharan 1352fae4b1eSJeenu Viswambharan# For Chain of Trust 1362fae4b1eSJeenu ViswambharanSAVE_KEYS := 0 1372fae4b1eSJeenu Viswambharan 1382fae4b1eSJeenu Viswambharan# Whether code and read-only data should be put on separate memory pages. The 1392fae4b1eSJeenu Viswambharan# platform Makefile is free to override this value. 1402fae4b1eSJeenu ViswambharanSEPARATE_CODE_AND_RODATA := 0 1412fae4b1eSJeenu Viswambharan 1422fae4b1eSJeenu Viswambharan# SPD choice 1432fae4b1eSJeenu ViswambharanSPD := none 1442fae4b1eSJeenu Viswambharan 1452fae4b1eSJeenu Viswambharan# Flag to introduce an infinite loop in BL1 just before it exits into the next 1462fae4b1eSJeenu Viswambharan# image. This is meant to help debugging the post-BL2 phase. 1472fae4b1eSJeenu ViswambharanSPIN_ON_BL1_EXIT := 0 1482fae4b1eSJeenu Viswambharan 1492fae4b1eSJeenu Viswambharan# Flags to build TF with Trusted Boot support 1502fae4b1eSJeenu ViswambharanTRUSTED_BOARD_BOOT := 0 1512fae4b1eSJeenu Viswambharan 1522fae4b1eSJeenu Viswambharan# Build option to choose whether Trusted firmware uses Coherent memory or not. 1532fae4b1eSJeenu ViswambharanUSE_COHERENT_MEM := 1 1542fae4b1eSJeenu Viswambharan 1552fae4b1eSJeenu Viswambharan# Build verbosity 1562fae4b1eSJeenu ViswambharanV := 0 157*bcc3c49cSSoby Mathew 158*bcc3c49cSSoby Mathew# Whether to enable D-Cache early during warm boot. This is usually 159*bcc3c49cSSoby Mathew# applicable for platforms wherein interconnect programming is not 160*bcc3c49cSSoby Mathew# required to enable cache coherency after warm reset (eg: single cluster 161*bcc3c49cSSoby Mathew# platforms). 162*bcc3c49cSSoby MathewWARMBOOT_ENABLE_DCACHE_EARLY := 0 163