12fae4b1eSJeenu Viswambharan# 2c877b414SJeenu Viswambharan# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 32fae4b1eSJeenu Viswambharan# 482cb2c1aSdp-arm# SPDX-License-Identifier: BSD-3-Clause 52fae4b1eSJeenu Viswambharan# 62fae4b1eSJeenu Viswambharan 72fae4b1eSJeenu Viswambharan# Default, static values for build variables, listed in alphabetic order. 82fae4b1eSJeenu Viswambharan# Dependencies between build options, if any, are handled in the top-level 92fae4b1eSJeenu Viswambharan# Makefile, after this file is included. This ensures that the former is better 102fae4b1eSJeenu Viswambharan# poised to handle dependencies, as all build variables would have a default 112fae4b1eSJeenu Viswambharan# value by then. 122fae4b1eSJeenu Viswambharan 132fae4b1eSJeenu Viswambharan# The AArch32 Secure Payload to be built as BL32 image 142fae4b1eSJeenu ViswambharanAARCH32_SP := none 152fae4b1eSJeenu Viswambharan 162fae4b1eSJeenu Viswambharan# The Target build architecture. Supported values are: aarch64, aarch32. 172fae4b1eSJeenu ViswambharanARCH := aarch64 182fae4b1eSJeenu Viswambharan 192fae4b1eSJeenu Viswambharan# Determine the version of ARM CCI product used in the platform. The platform 202fae4b1eSJeenu Viswambharan# port can change this value if needed. 212fae4b1eSJeenu ViswambharanARM_CCI_PRODUCT_ID := 400 222fae4b1eSJeenu Viswambharan 23c877b414SJeenu Viswambharan# ARM Architecture major and minor versions: 8.0 by default. 24c877b414SJeenu ViswambharanARM_ARCH_MAJOR := 8 25c877b414SJeenu ViswambharanARM_ARCH_MINOR := 0 26c877b414SJeenu Viswambharan 272fae4b1eSJeenu Viswambharan# Determine the version of ARM GIC architecture to use for interrupt management 282fae4b1eSJeenu Viswambharan# in EL3. The platform port can change this value if needed. 292fae4b1eSJeenu ViswambharanARM_GIC_ARCH := 2 302fae4b1eSJeenu Viswambharan 312fae4b1eSJeenu Viswambharan# Flag used to indicate if ASM_ASSERTION should be enabled for the build. 322fae4b1eSJeenu ViswambharanASM_ASSERTION := 0 332fae4b1eSJeenu Viswambharan 342fae4b1eSJeenu Viswambharan# Base commit to perform code check on 352fae4b1eSJeenu ViswambharanBASE_COMMIT := origin/master 362fae4b1eSJeenu Viswambharan 372fae4b1eSJeenu Viswambharan# By default, consider that the platform may release several CPUs out of reset. 382fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 392fae4b1eSJeenu ViswambharanCOLD_BOOT_SINGLE_CPU := 0 402fae4b1eSJeenu Viswambharan 412fae4b1eSJeenu Viswambharan# For Chain of Trust 422fae4b1eSJeenu ViswambharanCREATE_KEYS := 1 432fae4b1eSJeenu Viswambharan 442fae4b1eSJeenu Viswambharan# Build flag to include AArch32 registers in cpu context save and restore during 452fae4b1eSJeenu Viswambharan# world switch. This flag must be set to 0 for AArch64-only platforms. 462fae4b1eSJeenu ViswambharanCTX_INCLUDE_AARCH32_REGS := 1 472fae4b1eSJeenu Viswambharan 482fae4b1eSJeenu Viswambharan# Include FP registers in cpu context 492fae4b1eSJeenu ViswambharanCTX_INCLUDE_FPREGS := 0 502fae4b1eSJeenu Viswambharan 512fae4b1eSJeenu Viswambharan# Debug build 522fae4b1eSJeenu ViswambharanDEBUG := 0 532fae4b1eSJeenu Viswambharan 542fae4b1eSJeenu Viswambharan# Build platform 552fae4b1eSJeenu ViswambharanDEFAULT_PLAT := fvp 562fae4b1eSJeenu Viswambharan 572fae4b1eSJeenu Viswambharan# By default, use the -pedantic option in the gcc command line 582fae4b1eSJeenu ViswambharanDISABLE_PEDANTIC := 0 592fae4b1eSJeenu Viswambharan 602fae4b1eSJeenu Viswambharan# Flag to enable Performance Measurement Framework 612fae4b1eSJeenu ViswambharanENABLE_PMF := 0 622fae4b1eSJeenu Viswambharan 632fae4b1eSJeenu Viswambharan# Flag to enable PSCI STATs functionality 642fae4b1eSJeenu ViswambharanENABLE_PSCI_STAT := 0 652fae4b1eSJeenu Viswambharan 662fae4b1eSJeenu Viswambharan# Flag to enable runtime instrumentation using PMF 672fae4b1eSJeenu ViswambharanENABLE_RUNTIME_INSTRUMENTATION := 0 682fae4b1eSJeenu Viswambharan 6951faada7SDouglas Raillard# Flag to enable stack corruption protection 7051faada7SDouglas RaillardENABLE_STACK_PROTECTOR := 0 7151faada7SDouglas Raillard 722fae4b1eSJeenu Viswambharan# Build flag to treat usage of deprecated platform and framework APIs as error. 732fae4b1eSJeenu ViswambharanERROR_DEPRECATED := 0 742fae4b1eSJeenu Viswambharan 751c75d5dfSMasahiro Yamada# Byte alignment that each component in FIP is aligned to 761c75d5dfSMasahiro YamadaFIP_ALIGN := 0 771c75d5dfSMasahiro Yamada 782fae4b1eSJeenu Viswambharan# Default FIP file name 792fae4b1eSJeenu ViswambharanFIP_NAME := fip.bin 802fae4b1eSJeenu Viswambharan 812fae4b1eSJeenu Viswambharan# Default FWU_FIP file name 822fae4b1eSJeenu ViswambharanFWU_FIP_NAME := fwu_fip.bin 832fae4b1eSJeenu Viswambharan 842fae4b1eSJeenu Viswambharan# For Chain of Trust 852fae4b1eSJeenu ViswambharanGENERATE_COT := 0 862fae4b1eSJeenu Viswambharan 873c251af3SJeenu Viswambharan# Whether system coherency is managed in hardware, without explicit software 883c251af3SJeenu Viswambharan# operations. 893c251af3SJeenu ViswambharanHW_ASSISTED_COHERENCY := 0 903c251af3SJeenu Viswambharan 912fae4b1eSJeenu Viswambharan# Flag to enable new version of image loading 922fae4b1eSJeenu ViswambharanLOAD_IMAGE_V2 := 0 932fae4b1eSJeenu Viswambharan 942fae4b1eSJeenu Viswambharan# NS timer register save and restore 952fae4b1eSJeenu ViswambharanNS_TIMER_SWITCH := 0 962fae4b1eSJeenu Viswambharan 972fae4b1eSJeenu Viswambharan# Build PL011 UART driver in minimal generic UART mode 982fae4b1eSJeenu ViswambharanPL011_GENERIC_UART := 0 992fae4b1eSJeenu Viswambharan 1002fae4b1eSJeenu Viswambharan# By default, consider that the platform's reset address is not programmable. 1012fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 1022fae4b1eSJeenu ViswambharanPROGRAMMABLE_RESET_ADDRESS := 0 1032fae4b1eSJeenu Viswambharan 1042fae4b1eSJeenu Viswambharan# Flag used to choose the power state format viz Extended State-ID or the 1052fae4b1eSJeenu Viswambharan# Original format. 1062fae4b1eSJeenu ViswambharanPSCI_EXTENDED_STATE_ID := 0 1072fae4b1eSJeenu Viswambharan 1082fae4b1eSJeenu Viswambharan# By default, BL1 acts as the reset handler, not BL31 1092fae4b1eSJeenu ViswambharanRESET_TO_BL31 := 0 1102fae4b1eSJeenu Viswambharan 1112fae4b1eSJeenu Viswambharan# For Chain of Trust 1122fae4b1eSJeenu ViswambharanSAVE_KEYS := 0 1132fae4b1eSJeenu Viswambharan 1142fae4b1eSJeenu Viswambharan# Whether code and read-only data should be put on separate memory pages. The 1152fae4b1eSJeenu Viswambharan# platform Makefile is free to override this value. 1162fae4b1eSJeenu ViswambharanSEPARATE_CODE_AND_RODATA := 0 1172fae4b1eSJeenu Viswambharan 1182fae4b1eSJeenu Viswambharan# SPD choice 1192fae4b1eSJeenu ViswambharanSPD := none 1202fae4b1eSJeenu Viswambharan 1212fae4b1eSJeenu Viswambharan# Flag to introduce an infinite loop in BL1 just before it exits into the next 1222fae4b1eSJeenu Viswambharan# image. This is meant to help debugging the post-BL2 phase. 1232fae4b1eSJeenu ViswambharanSPIN_ON_BL1_EXIT := 0 1242fae4b1eSJeenu Viswambharan 1252fae4b1eSJeenu Viswambharan# Flags to build TF with Trusted Boot support 1262fae4b1eSJeenu ViswambharanTRUSTED_BOARD_BOOT := 0 1272fae4b1eSJeenu Viswambharan 1282fae4b1eSJeenu Viswambharan# Build option to choose whether Trusted firmware uses Coherent memory or not. 1292fae4b1eSJeenu ViswambharanUSE_COHERENT_MEM := 1 1302fae4b1eSJeenu Viswambharan 131*bb41eb7aSMasahiro Yamada# Use tbbr_oid.h instead of platform_oid.h 132*bb41eb7aSMasahiro YamadaUSE_TBBR_DEFS = $(ERROR_DEPRECATED) 133*bb41eb7aSMasahiro Yamada 1342fae4b1eSJeenu Viswambharan# Build verbosity 1352fae4b1eSJeenu ViswambharanV := 0 136bcc3c49cSSoby Mathew 137bcc3c49cSSoby Mathew# Whether to enable D-Cache early during warm boot. This is usually 138bcc3c49cSSoby Mathew# applicable for platforms wherein interconnect programming is not 139bcc3c49cSSoby Mathew# required to enable cache coherency after warm reset (eg: single cluster 140bcc3c49cSSoby Mathew# platforms). 141bcc3c49cSSoby MathewWARMBOOT_ENABLE_DCACHE_EARLY := 0 142