12fae4b1eSJeenu Viswambharan# 2c877b414SJeenu Viswambharan# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 32fae4b1eSJeenu Viswambharan# 482cb2c1aSdp-arm# SPDX-License-Identifier: BSD-3-Clause 52fae4b1eSJeenu Viswambharan# 62fae4b1eSJeenu Viswambharan 72fae4b1eSJeenu Viswambharan# Default, static values for build variables, listed in alphabetic order. 82fae4b1eSJeenu Viswambharan# Dependencies between build options, if any, are handled in the top-level 92fae4b1eSJeenu Viswambharan# Makefile, after this file is included. This ensures that the former is better 102fae4b1eSJeenu Viswambharan# poised to handle dependencies, as all build variables would have a default 112fae4b1eSJeenu Viswambharan# value by then. 122fae4b1eSJeenu Viswambharan 132fae4b1eSJeenu Viswambharan# The AArch32 Secure Payload to be built as BL32 image 142fae4b1eSJeenu ViswambharanAARCH32_SP := none 152fae4b1eSJeenu Viswambharan 162fae4b1eSJeenu Viswambharan# The Target build architecture. Supported values are: aarch64, aarch32. 172fae4b1eSJeenu ViswambharanARCH := aarch64 182fae4b1eSJeenu Viswambharan 19c877b414SJeenu Viswambharan# ARM Architecture major and minor versions: 8.0 by default. 20c877b414SJeenu ViswambharanARM_ARCH_MAJOR := 8 21c877b414SJeenu ViswambharanARM_ARCH_MINOR := 0 22c877b414SJeenu Viswambharan 232fae4b1eSJeenu Viswambharan# Determine the version of ARM GIC architecture to use for interrupt management 242fae4b1eSJeenu Viswambharan# in EL3. The platform port can change this value if needed. 252fae4b1eSJeenu ViswambharanARM_GIC_ARCH := 2 262fae4b1eSJeenu Viswambharan 272fae4b1eSJeenu Viswambharan# Base commit to perform code check on 282fae4b1eSJeenu ViswambharanBASE_COMMIT := origin/master 292fae4b1eSJeenu Viswambharan 302fae4b1eSJeenu Viswambharan# By default, consider that the platform may release several CPUs out of reset. 312fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 322fae4b1eSJeenu ViswambharanCOLD_BOOT_SINGLE_CPU := 0 332fae4b1eSJeenu Viswambharan 34*3429c77aSJulius Werner# Flag to compile in coreboot support code. Exclude by default. The coreboot 35*3429c77aSJulius Werner# Makefile system will set this when compiling TF as part of a coreboot image. 36*3429c77aSJulius WernerCOREBOOT := 0 37*3429c77aSJulius Werner 382fae4b1eSJeenu Viswambharan# For Chain of Trust 392fae4b1eSJeenu ViswambharanCREATE_KEYS := 1 402fae4b1eSJeenu Viswambharan 412fae4b1eSJeenu Viswambharan# Build flag to include AArch32 registers in cpu context save and restore during 422fae4b1eSJeenu Viswambharan# world switch. This flag must be set to 0 for AArch64-only platforms. 432fae4b1eSJeenu ViswambharanCTX_INCLUDE_AARCH32_REGS := 1 442fae4b1eSJeenu Viswambharan 452fae4b1eSJeenu Viswambharan# Include FP registers in cpu context 462fae4b1eSJeenu ViswambharanCTX_INCLUDE_FPREGS := 0 472fae4b1eSJeenu Viswambharan 482fae4b1eSJeenu Viswambharan# Debug build 492fae4b1eSJeenu ViswambharanDEBUG := 0 502fae4b1eSJeenu Viswambharan 512fae4b1eSJeenu Viswambharan# Build platform 522fae4b1eSJeenu ViswambharanDEFAULT_PLAT := fvp 532fae4b1eSJeenu Viswambharan 542fae4b1eSJeenu Viswambharan# Flag to enable Performance Measurement Framework 552fae4b1eSJeenu ViswambharanENABLE_PMF := 0 562fae4b1eSJeenu Viswambharan 572fae4b1eSJeenu Viswambharan# Flag to enable PSCI STATs functionality 582fae4b1eSJeenu ViswambharanENABLE_PSCI_STAT := 0 592fae4b1eSJeenu Viswambharan 602fae4b1eSJeenu Viswambharan# Flag to enable runtime instrumentation using PMF 612fae4b1eSJeenu ViswambharanENABLE_RUNTIME_INSTRUMENTATION := 0 622fae4b1eSJeenu Viswambharan 6351faada7SDouglas Raillard# Flag to enable stack corruption protection 6451faada7SDouglas RaillardENABLE_STACK_PROTECTOR := 0 6551faada7SDouglas Raillard 6621b818c0SJeenu Viswambharan# Flag to enable exception handling in EL3 6721b818c0SJeenu ViswambharanEL3_EXCEPTION_HANDLING := 0 6821b818c0SJeenu Viswambharan 692fae4b1eSJeenu Viswambharan# Build flag to treat usage of deprecated platform and framework APIs as error. 702fae4b1eSJeenu ViswambharanERROR_DEPRECATED := 0 712fae4b1eSJeenu Viswambharan 721c75d5dfSMasahiro Yamada# Byte alignment that each component in FIP is aligned to 731c75d5dfSMasahiro YamadaFIP_ALIGN := 0 741c75d5dfSMasahiro Yamada 752fae4b1eSJeenu Viswambharan# Default FIP file name 762fae4b1eSJeenu ViswambharanFIP_NAME := fip.bin 772fae4b1eSJeenu Viswambharan 782fae4b1eSJeenu Viswambharan# Default FWU_FIP file name 792fae4b1eSJeenu ViswambharanFWU_FIP_NAME := fwu_fip.bin 802fae4b1eSJeenu Viswambharan 812fae4b1eSJeenu Viswambharan# For Chain of Trust 822fae4b1eSJeenu ViswambharanGENERATE_COT := 0 832fae4b1eSJeenu Viswambharan 8474dce7faSJeenu Viswambharan# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 8574dce7faSJeenu Viswambharan# default, they are for Secure EL1. 8674dce7faSJeenu ViswambharanGICV2_G0_FOR_EL3 := 0 8774dce7faSJeenu Viswambharan 883c251af3SJeenu Viswambharan# Whether system coherency is managed in hardware, without explicit software 893c251af3SJeenu Viswambharan# operations. 903c251af3SJeenu ViswambharanHW_ASSISTED_COHERENCY := 0 913c251af3SJeenu Viswambharan 922091755cSSoby Mathew# Set the default algorithm for the generation of Trusted Board Boot keys 932091755cSSoby MathewKEY_ALG := rsa 942091755cSSoby Mathew 952fae4b1eSJeenu Viswambharan# Flag to enable new version of image loading 962fae4b1eSJeenu ViswambharanLOAD_IMAGE_V2 := 0 972fae4b1eSJeenu Viswambharan 989536bae6SJulius Werner# Use the new console API that allows registering more than one console instance 999536bae6SJulius Werner# at once. Use = instead of := to dynamically default to ERROR_DEPRECATED. 1009536bae6SJulius WernerMULTI_CONSOLE_API = $(ERROR_DEPRECATED) 1019536bae6SJulius Werner 1022fae4b1eSJeenu Viswambharan# NS timer register save and restore 1032fae4b1eSJeenu ViswambharanNS_TIMER_SWITCH := 0 1042fae4b1eSJeenu Viswambharan 1052fae4b1eSJeenu Viswambharan# Build PL011 UART driver in minimal generic UART mode 1062fae4b1eSJeenu ViswambharanPL011_GENERIC_UART := 0 1072fae4b1eSJeenu Viswambharan 1082fae4b1eSJeenu Viswambharan# By default, consider that the platform's reset address is not programmable. 1092fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 1102fae4b1eSJeenu ViswambharanPROGRAMMABLE_RESET_ADDRESS := 0 1112fae4b1eSJeenu Viswambharan 1122fae4b1eSJeenu Viswambharan# Flag used to choose the power state format viz Extended State-ID or the 1132fae4b1eSJeenu Viswambharan# Original format. 1142fae4b1eSJeenu ViswambharanPSCI_EXTENDED_STATE_ID := 0 1152fae4b1eSJeenu Viswambharan 1162fae4b1eSJeenu Viswambharan# By default, BL1 acts as the reset handler, not BL31 1172fae4b1eSJeenu ViswambharanRESET_TO_BL31 := 0 1182fae4b1eSJeenu Viswambharan 1192fae4b1eSJeenu Viswambharan# For Chain of Trust 1202fae4b1eSJeenu ViswambharanSAVE_KEYS := 0 1212fae4b1eSJeenu Viswambharan 122b7cb133eSJeenu Viswambharan# Software Delegated Exception support 123b7cb133eSJeenu ViswambharanSDEI_SUPPORT := 0 124b7cb133eSJeenu Viswambharan 1252fae4b1eSJeenu Viswambharan# Whether code and read-only data should be put on separate memory pages. The 1262fae4b1eSJeenu Viswambharan# platform Makefile is free to override this value. 1272fae4b1eSJeenu ViswambharanSEPARATE_CODE_AND_RODATA := 0 1282fae4b1eSJeenu Viswambharan 1292fae4b1eSJeenu Viswambharan# SPD choice 1302fae4b1eSJeenu ViswambharanSPD := none 1312fae4b1eSJeenu Viswambharan 1322fccb228SAntonio Nino Diaz# For including the Secure Partition Manager 1332fccb228SAntonio Nino DiazENABLE_SPM := 0 1342fccb228SAntonio Nino Diaz 1352fae4b1eSJeenu Viswambharan# Flag to introduce an infinite loop in BL1 just before it exits into the next 1362fae4b1eSJeenu Viswambharan# image. This is meant to help debugging the post-BL2 phase. 1372fae4b1eSJeenu ViswambharanSPIN_ON_BL1_EXIT := 0 1382fae4b1eSJeenu Viswambharan 1392fae4b1eSJeenu Viswambharan# Flags to build TF with Trusted Boot support 1402fae4b1eSJeenu ViswambharanTRUSTED_BOARD_BOOT := 0 1412fae4b1eSJeenu Viswambharan 1422fae4b1eSJeenu Viswambharan# Build option to choose whether Trusted firmware uses Coherent memory or not. 1432fae4b1eSJeenu ViswambharanUSE_COHERENT_MEM := 1 1442fae4b1eSJeenu Viswambharan 145bb41eb7aSMasahiro Yamada# Use tbbr_oid.h instead of platform_oid.h 146bb41eb7aSMasahiro YamadaUSE_TBBR_DEFS = $(ERROR_DEPRECATED) 147bb41eb7aSMasahiro Yamada 1482fae4b1eSJeenu Viswambharan# Build verbosity 1492fae4b1eSJeenu ViswambharanV := 0 150bcc3c49cSSoby Mathew 151bcc3c49cSSoby Mathew# Whether to enable D-Cache early during warm boot. This is usually 152bcc3c49cSSoby Mathew# applicable for platforms wherein interconnect programming is not 153bcc3c49cSSoby Mathew# required to enable cache coherency after warm reset (eg: single cluster 154bcc3c49cSSoby Mathew# platforms). 155bcc3c49cSSoby MathewWARMBOOT_ENABLE_DCACHE_EARLY := 0 156d832aee9Sdp-arm 157c776deedSDimitris Papastamos# Build option to enable/disable the Statistical Profiling Extensions 158d832aee9Sdp-armENABLE_SPE_FOR_LOWER_ELS := 1 159d832aee9Sdp-arm 160c776deedSDimitris Papastamos# SPE is only supported on AArch64 so disable it on AArch32. 161d832aee9Sdp-armifeq (${ARCH},aarch32) 162d832aee9Sdp-arm override ENABLE_SPE_FOR_LOWER_ELS := 0 163d832aee9Sdp-armendif 1640319a977SDimitris Papastamos 1650319a977SDimitris PapastamosENABLE_AMU := 0 1661a853370SDavid Cunado 1671a853370SDavid Cunado# By default, enable Scalable Vector Extension if implemented for Non-secure 1681a853370SDavid Cunado# lower ELs 1691a853370SDavid Cunado# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 1701a853370SDavid Cunadoifneq (${ARCH},aarch32) 1711a853370SDavid Cunado ENABLE_SVE_FOR_NS := 1 1721a853370SDavid Cunadoelse 1731a853370SDavid Cunado override ENABLE_SVE_FOR_NS := 0 1741a853370SDavid Cunadoendif 175