1*2fae4b1eSJeenu Viswambharan# 2*2fae4b1eSJeenu Viswambharan# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*2fae4b1eSJeenu Viswambharan# 4*2fae4b1eSJeenu Viswambharan# Redistribution and use in source and binary forms, with or without 5*2fae4b1eSJeenu Viswambharan# modification, are permitted provided that the following conditions are met: 6*2fae4b1eSJeenu Viswambharan# 7*2fae4b1eSJeenu Viswambharan# Redistributions of source code must retain the above copyright notice, this 8*2fae4b1eSJeenu Viswambharan# list of conditions and the following disclaimer. 9*2fae4b1eSJeenu Viswambharan# 10*2fae4b1eSJeenu Viswambharan# Redistributions in binary form must reproduce the above copyright notice, 11*2fae4b1eSJeenu Viswambharan# this list of conditions and the following disclaimer in the documentation 12*2fae4b1eSJeenu Viswambharan# and/or other materials provided with the distribution. 13*2fae4b1eSJeenu Viswambharan# 14*2fae4b1eSJeenu Viswambharan# Neither the name of ARM nor the names of its contributors may be used 15*2fae4b1eSJeenu Viswambharan# to endorse or promote products derived from this software without specific 16*2fae4b1eSJeenu Viswambharan# prior written permission. 17*2fae4b1eSJeenu Viswambharan# 18*2fae4b1eSJeenu Viswambharan# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*2fae4b1eSJeenu Viswambharan# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*2fae4b1eSJeenu Viswambharan# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*2fae4b1eSJeenu Viswambharan# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*2fae4b1eSJeenu Viswambharan# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*2fae4b1eSJeenu Viswambharan# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*2fae4b1eSJeenu Viswambharan# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*2fae4b1eSJeenu Viswambharan# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*2fae4b1eSJeenu Viswambharan# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*2fae4b1eSJeenu Viswambharan# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*2fae4b1eSJeenu Viswambharan# POSSIBILITY OF SUCH DAMAGE. 29*2fae4b1eSJeenu Viswambharan# 30*2fae4b1eSJeenu Viswambharan 31*2fae4b1eSJeenu Viswambharan# Default, static values for build variables, listed in alphabetic order. 32*2fae4b1eSJeenu Viswambharan# Dependencies between build options, if any, are handled in the top-level 33*2fae4b1eSJeenu Viswambharan# Makefile, after this file is included. This ensures that the former is better 34*2fae4b1eSJeenu Viswambharan# poised to handle dependencies, as all build variables would have a default 35*2fae4b1eSJeenu Viswambharan# value by then. 36*2fae4b1eSJeenu Viswambharan 37*2fae4b1eSJeenu Viswambharan# The AArch32 Secure Payload to be built as BL32 image 38*2fae4b1eSJeenu ViswambharanAARCH32_SP := none 39*2fae4b1eSJeenu Viswambharan 40*2fae4b1eSJeenu Viswambharan# The Target build architecture. Supported values are: aarch64, aarch32. 41*2fae4b1eSJeenu ViswambharanARCH := aarch64 42*2fae4b1eSJeenu Viswambharan 43*2fae4b1eSJeenu Viswambharan# Determine the version of ARM CCI product used in the platform. The platform 44*2fae4b1eSJeenu Viswambharan# port can change this value if needed. 45*2fae4b1eSJeenu ViswambharanARM_CCI_PRODUCT_ID := 400 46*2fae4b1eSJeenu Viswambharan 47*2fae4b1eSJeenu Viswambharan# Determine the version of ARM GIC architecture to use for interrupt management 48*2fae4b1eSJeenu Viswambharan# in EL3. The platform port can change this value if needed. 49*2fae4b1eSJeenu ViswambharanARM_GIC_ARCH := 2 50*2fae4b1eSJeenu Viswambharan 51*2fae4b1eSJeenu Viswambharan# Flag used to indicate if ASM_ASSERTION should be enabled for the build. 52*2fae4b1eSJeenu ViswambharanASM_ASSERTION := 0 53*2fae4b1eSJeenu Viswambharan 54*2fae4b1eSJeenu Viswambharan# Base commit to perform code check on 55*2fae4b1eSJeenu ViswambharanBASE_COMMIT := origin/master 56*2fae4b1eSJeenu Viswambharan 57*2fae4b1eSJeenu Viswambharan# By default, consider that the platform may release several CPUs out of reset. 58*2fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 59*2fae4b1eSJeenu ViswambharanCOLD_BOOT_SINGLE_CPU := 0 60*2fae4b1eSJeenu Viswambharan 61*2fae4b1eSJeenu Viswambharan# For Chain of Trust 62*2fae4b1eSJeenu ViswambharanCREATE_KEYS := 1 63*2fae4b1eSJeenu Viswambharan 64*2fae4b1eSJeenu Viswambharan# Build flag to include AArch32 registers in cpu context save and restore during 65*2fae4b1eSJeenu Viswambharan# world switch. This flag must be set to 0 for AArch64-only platforms. 66*2fae4b1eSJeenu ViswambharanCTX_INCLUDE_AARCH32_REGS := 1 67*2fae4b1eSJeenu Viswambharan 68*2fae4b1eSJeenu Viswambharan# Include FP registers in cpu context 69*2fae4b1eSJeenu ViswambharanCTX_INCLUDE_FPREGS := 0 70*2fae4b1eSJeenu Viswambharan 71*2fae4b1eSJeenu Viswambharan# Debug build 72*2fae4b1eSJeenu ViswambharanDEBUG := 0 73*2fae4b1eSJeenu Viswambharan 74*2fae4b1eSJeenu Viswambharan# Build platform 75*2fae4b1eSJeenu ViswambharanDEFAULT_PLAT := fvp 76*2fae4b1eSJeenu Viswambharan 77*2fae4b1eSJeenu Viswambharan# By default, use the -pedantic option in the gcc command line 78*2fae4b1eSJeenu ViswambharanDISABLE_PEDANTIC := 0 79*2fae4b1eSJeenu Viswambharan 80*2fae4b1eSJeenu Viswambharan# Flag to enable Performance Measurement Framework 81*2fae4b1eSJeenu ViswambharanENABLE_PMF := 0 82*2fae4b1eSJeenu Viswambharan 83*2fae4b1eSJeenu Viswambharan# Flag to enable PSCI STATs functionality 84*2fae4b1eSJeenu ViswambharanENABLE_PSCI_STAT := 0 85*2fae4b1eSJeenu Viswambharan 86*2fae4b1eSJeenu Viswambharan# Flag to enable runtime instrumentation using PMF 87*2fae4b1eSJeenu ViswambharanENABLE_RUNTIME_INSTRUMENTATION := 0 88*2fae4b1eSJeenu Viswambharan 89*2fae4b1eSJeenu Viswambharan# Build flag to treat usage of deprecated platform and framework APIs as error. 90*2fae4b1eSJeenu ViswambharanERROR_DEPRECATED := 0 91*2fae4b1eSJeenu Viswambharan 92*2fae4b1eSJeenu Viswambharan# Default FIP file name 93*2fae4b1eSJeenu ViswambharanFIP_NAME := fip.bin 94*2fae4b1eSJeenu Viswambharan 95*2fae4b1eSJeenu Viswambharan# Default FWU_FIP file name 96*2fae4b1eSJeenu ViswambharanFWU_FIP_NAME := fwu_fip.bin 97*2fae4b1eSJeenu Viswambharan 98*2fae4b1eSJeenu Viswambharan# For Chain of Trust 99*2fae4b1eSJeenu ViswambharanGENERATE_COT := 0 100*2fae4b1eSJeenu Viswambharan 101*2fae4b1eSJeenu Viswambharan# Flag to enable new version of image loading 102*2fae4b1eSJeenu ViswambharanLOAD_IMAGE_V2 := 0 103*2fae4b1eSJeenu Viswambharan 104*2fae4b1eSJeenu Viswambharan# NS timer register save and restore 105*2fae4b1eSJeenu ViswambharanNS_TIMER_SWITCH := 0 106*2fae4b1eSJeenu Viswambharan 107*2fae4b1eSJeenu Viswambharan# Build PL011 UART driver in minimal generic UART mode 108*2fae4b1eSJeenu ViswambharanPL011_GENERIC_UART := 0 109*2fae4b1eSJeenu Viswambharan 110*2fae4b1eSJeenu Viswambharan# By default, consider that the platform's reset address is not programmable. 111*2fae4b1eSJeenu Viswambharan# The platform Makefile is free to override this value. 112*2fae4b1eSJeenu ViswambharanPROGRAMMABLE_RESET_ADDRESS := 0 113*2fae4b1eSJeenu Viswambharan 114*2fae4b1eSJeenu Viswambharan# Flag used to choose the power state format viz Extended State-ID or the 115*2fae4b1eSJeenu Viswambharan# Original format. 116*2fae4b1eSJeenu ViswambharanPSCI_EXTENDED_STATE_ID := 0 117*2fae4b1eSJeenu Viswambharan 118*2fae4b1eSJeenu Viswambharan# By default, BL1 acts as the reset handler, not BL31 119*2fae4b1eSJeenu ViswambharanRESET_TO_BL31 := 0 120*2fae4b1eSJeenu Viswambharan 121*2fae4b1eSJeenu Viswambharan# For Chain of Trust 122*2fae4b1eSJeenu ViswambharanSAVE_KEYS := 0 123*2fae4b1eSJeenu Viswambharan 124*2fae4b1eSJeenu Viswambharan# Whether code and read-only data should be put on separate memory pages. The 125*2fae4b1eSJeenu Viswambharan# platform Makefile is free to override this value. 126*2fae4b1eSJeenu ViswambharanSEPARATE_CODE_AND_RODATA := 0 127*2fae4b1eSJeenu Viswambharan 128*2fae4b1eSJeenu Viswambharan# SPD choice 129*2fae4b1eSJeenu ViswambharanSPD := none 130*2fae4b1eSJeenu Viswambharan 131*2fae4b1eSJeenu Viswambharan# Flag to introduce an infinite loop in BL1 just before it exits into the next 132*2fae4b1eSJeenu Viswambharan# image. This is meant to help debugging the post-BL2 phase. 133*2fae4b1eSJeenu ViswambharanSPIN_ON_BL1_EXIT := 0 134*2fae4b1eSJeenu Viswambharan 135*2fae4b1eSJeenu Viswambharan# Flags to build TF with Trusted Boot support 136*2fae4b1eSJeenu ViswambharanTRUSTED_BOARD_BOOT := 0 137*2fae4b1eSJeenu Viswambharan 138*2fae4b1eSJeenu Viswambharan# Build option to choose whether Trusted firmware uses Coherent memory or not. 139*2fae4b1eSJeenu ViswambharanUSE_COHERENT_MEM := 1 140*2fae4b1eSJeenu Viswambharan 141*2fae4b1eSJeenu Viswambharan# Build verbosity 142*2fae4b1eSJeenu ViswambharanV := 0 143