1 /* 2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <stdint.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <lib/cassert.h> 15 #include <lib/utils_def.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 18 #include "../xlat_tables_private.h" 19 20 /* 21 * Returns true if the provided granule size is supported, false otherwise. 22 */ 23 bool xlat_arch_is_granule_size_supported(size_t size) 24 { 25 unsigned int tgranx; 26 27 if (size == PAGE_SIZE_4KB) { 28 tgranx = read_id_aa64mmfr0_el0_tgran4_field(); 29 /* MSB of TGRAN4 field will be '1' for unsupported feature */ 30 return (tgranx < 8U); 31 } else if (size == PAGE_SIZE_16KB) { 32 tgranx = read_id_aa64mmfr0_el0_tgran16_field(); 33 return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED); 34 } else if (size == PAGE_SIZE_64KB) { 35 tgranx = read_id_aa64mmfr0_el0_tgran64_field(); 36 /* MSB of TGRAN64 field will be '1' for unsupported feature */ 37 return (tgranx < 8U); 38 } else { 39 return false; 40 } 41 } 42 43 size_t xlat_arch_get_max_supported_granule_size(void) 44 { 45 if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { 46 return PAGE_SIZE_64KB; 47 } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { 48 return PAGE_SIZE_16KB; 49 } else { 50 assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); 51 return PAGE_SIZE_4KB; 52 } 53 } 54 55 /* 56 * Determine the physical address space encoded in the 'attr' parameter. 57 * 58 * The physical address will fall into one of four spaces; secure, 59 * nonsecure, root, or realm if RME is enabled, or one of two spaces; 60 * secure and nonsecure otherwise. 61 */ 62 uint32_t xlat_arch_get_pas(uint32_t attr) 63 { 64 uint32_t pas = MT_PAS(attr); 65 66 switch (pas) { 67 #if ENABLE_RME 68 /* TTD.NSE = 1 and TTD.NS = 1 for Realm PAS */ 69 case MT_REALM: 70 return LOWER_ATTRS(EL3_S1_NSE | NS); 71 /* TTD.NSE = 1 and TTD.NS = 0 for Root PAS */ 72 case MT_ROOT: 73 return LOWER_ATTRS(EL3_S1_NSE); 74 #endif 75 case MT_NS: 76 return LOWER_ATTRS(NS); 77 default: /* MT_SECURE */ 78 return 0U; 79 } 80 } 81 82 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 83 { 84 /* Physical address can't exceed 48 bits */ 85 assert((max_addr & ADDR_MASK_48_TO_63) == 0U); 86 87 /* 48 bits address */ 88 if ((max_addr & ADDR_MASK_44_TO_47) != 0U) 89 return TCR_PS_BITS_256TB; 90 91 /* 44 bits address */ 92 if ((max_addr & ADDR_MASK_42_TO_43) != 0U) 93 return TCR_PS_BITS_16TB; 94 95 /* 42 bits address */ 96 if ((max_addr & ADDR_MASK_40_TO_41) != 0U) 97 return TCR_PS_BITS_4TB; 98 99 /* 40 bits address */ 100 if ((max_addr & ADDR_MASK_36_TO_39) != 0U) 101 return TCR_PS_BITS_1TB; 102 103 /* 36 bits address */ 104 if ((max_addr & ADDR_MASK_32_TO_35) != 0U) 105 return TCR_PS_BITS_64GB; 106 107 return TCR_PS_BITS_4GB; 108 } 109 110 #if ENABLE_ASSERTIONS 111 /* 112 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 113 * supported in ARMv8.2 onwards. 114 */ 115 static const unsigned int pa_range_bits_arr[] = { 116 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 117 PARANGE_0101, PARANGE_0110 118 }; 119 120 unsigned long long xlat_arch_get_max_supported_pa(void) 121 { 122 u_register_t pa_range = read_id_aa64mmfr0_el1() & 123 ID_AA64MMFR0_EL1_PARANGE_MASK; 124 125 /* All other values are reserved */ 126 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 127 128 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 129 } 130 131 /* 132 * Return minimum virtual address space size supported by the architecture 133 */ 134 uintptr_t xlat_get_min_virt_addr_space_size(void) 135 { 136 uintptr_t ret; 137 138 if (is_armv8_4_ttst_present()) 139 ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST; 140 else 141 ret = MIN_VIRT_ADDR_SPACE_SIZE; 142 143 return ret; 144 } 145 #endif /* ENABLE_ASSERTIONS*/ 146 147 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 148 { 149 if (ctx->xlat_regime == EL1_EL0_REGIME) { 150 assert(xlat_arch_current_el() >= 1U); 151 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; 152 } else if (ctx->xlat_regime == EL2_REGIME) { 153 assert(xlat_arch_current_el() >= 2U); 154 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; 155 } else { 156 assert(ctx->xlat_regime == EL3_REGIME); 157 assert(xlat_arch_current_el() >= 3U); 158 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; 159 } 160 } 161 162 bool is_dcache_enabled(void) 163 { 164 unsigned int el = get_current_el_maybe_constant(); 165 166 if (el == 1U) { 167 return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; 168 } else if (el == 2U) { 169 return (read_sctlr_el2() & SCTLR_C_BIT) != 0U; 170 } else { 171 return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; 172 } 173 } 174 175 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 176 { 177 if (xlat_regime == EL1_EL0_REGIME) { 178 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); 179 } else { 180 assert((xlat_regime == EL2_REGIME) || 181 (xlat_regime == EL3_REGIME)); 182 return UPPER_ATTRS(XN); 183 } 184 } 185 186 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 187 { 188 /* 189 * Ensure the translation table write has drained into memory before 190 * invalidating the TLB entry. 191 */ 192 dsbishst(); 193 194 /* 195 * This function only supports invalidation of TLB entries for the EL3 196 * and EL1&0 translation regimes. 197 * 198 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 199 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 200 */ 201 if (xlat_regime == EL1_EL0_REGIME) { 202 assert(xlat_arch_current_el() >= 1U); 203 tlbivaae1is(TLBI_ADDR(va)); 204 } else if (xlat_regime == EL2_REGIME) { 205 assert(xlat_arch_current_el() >= 2U); 206 tlbivae2is(TLBI_ADDR(va)); 207 } else { 208 assert(xlat_regime == EL3_REGIME); 209 assert(xlat_arch_current_el() >= 3U); 210 tlbivae3is(TLBI_ADDR(va)); 211 } 212 } 213 214 void xlat_arch_tlbi_va_sync(void) 215 { 216 /* 217 * A TLB maintenance instruction can complete at any time after 218 * it is issued, but is only guaranteed to be complete after the 219 * execution of DSB by the PE that executed the TLB maintenance 220 * instruction. After the TLB invalidate instruction is 221 * complete, no new memory accesses using the invalidated TLB 222 * entries will be observed by any observer of the system 223 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 224 * "Ordering and completion of TLB maintenance instructions". 225 */ 226 dsbish(); 227 228 /* 229 * The effects of a completed TLB maintenance instruction are 230 * only guaranteed to be visible on the PE that executed the 231 * instruction after the execution of an ISB instruction by the 232 * PE that executed the TLB maintenance instruction. 233 */ 234 isb(); 235 } 236 237 unsigned int xlat_arch_current_el(void) 238 { 239 unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); 240 241 assert(el > 0U); 242 243 return el; 244 } 245 246 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 247 const uint64_t *base_table, unsigned long long max_pa, 248 uintptr_t max_va, int xlat_regime) 249 { 250 uint64_t mair, ttbr0, tcr; 251 uintptr_t virtual_addr_space_size; 252 253 /* Set attributes in the right indices of the MAIR. */ 254 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 255 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 256 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 257 258 /* 259 * Limit the input address ranges and memory region sizes translated 260 * using TTBR0 to the given virtual address space size. 261 */ 262 assert(max_va < ((uint64_t)UINTPTR_MAX)); 263 264 virtual_addr_space_size = (uintptr_t)max_va + 1U; 265 266 assert(virtual_addr_space_size >= 267 xlat_get_min_virt_addr_space_size()); 268 assert(virtual_addr_space_size <= MAX_VIRT_ADDR_SPACE_SIZE); 269 assert(IS_POWER_OF_TWO(virtual_addr_space_size)); 270 271 /* 272 * __builtin_ctzll(0) is undefined but here we are guaranteed that 273 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 274 */ 275 int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); 276 277 tcr = (uint64_t)t0sz << TCR_T0SZ_SHIFT; 278 279 /* 280 * Set the cacheability and shareability attributes for memory 281 * associated with translation table walks. 282 */ 283 if ((flags & XLAT_TABLE_NC) != 0U) { 284 /* Inner & outer non-cacheable non-shareable. */ 285 tcr |= TCR_SH_NON_SHAREABLE | 286 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 287 } else { 288 /* Inner & outer WBWA & shareable. */ 289 tcr |= TCR_SH_INNER_SHAREABLE | 290 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 291 } 292 293 /* 294 * It is safer to restrict the max physical address accessible by the 295 * hardware as much as possible. 296 */ 297 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 298 299 if (xlat_regime == EL1_EL0_REGIME) { 300 /* 301 * TCR_EL1.EPD1: Disable translation table walk for addresses 302 * that are translated using TTBR1_EL1. 303 */ 304 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 305 } else if (xlat_regime == EL2_REGIME) { 306 tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT); 307 } else { 308 assert(xlat_regime == EL3_REGIME); 309 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 310 } 311 312 /* Set TTBR bits as well */ 313 ttbr0 = (uint64_t) base_table; 314 315 if (is_armv8_2_ttcnp_present()) { 316 /* Enable CnP bit so as to share page tables with all PEs. */ 317 ttbr0 |= TTBR_CNP_BIT; 318 } 319 320 params[MMU_CFG_MAIR] = mair; 321 params[MMU_CFG_TCR] = tcr; 322 params[MMU_CFG_TTBR0] = ttbr0; 323 } 324