1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <stdint.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <lib/cassert.h> 15 #include <lib/utils_def.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 18 #include "../xlat_tables_private.h" 19 20 /* 21 * Returns true if the provided granule size is supported, false otherwise. 22 */ 23 bool xlat_arch_is_granule_size_supported(size_t size) 24 { 25 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 26 27 if (size == PAGE_SIZE_4KB) { 28 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 29 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 30 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 31 } else if (size == PAGE_SIZE_16KB) { 32 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 33 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 34 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 35 } else if (size == PAGE_SIZE_64KB) { 36 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 37 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 38 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 39 } else { 40 return 0; 41 } 42 } 43 44 size_t xlat_arch_get_max_supported_granule_size(void) 45 { 46 if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { 47 return PAGE_SIZE_64KB; 48 } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { 49 return PAGE_SIZE_16KB; 50 } else { 51 assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); 52 return PAGE_SIZE_4KB; 53 } 54 } 55 56 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 57 { 58 /* Physical address can't exceed 48 bits */ 59 assert((max_addr & ADDR_MASK_48_TO_63) == 0U); 60 61 /* 48 bits address */ 62 if ((max_addr & ADDR_MASK_44_TO_47) != 0U) 63 return TCR_PS_BITS_256TB; 64 65 /* 44 bits address */ 66 if ((max_addr & ADDR_MASK_42_TO_43) != 0U) 67 return TCR_PS_BITS_16TB; 68 69 /* 42 bits address */ 70 if ((max_addr & ADDR_MASK_40_TO_41) != 0U) 71 return TCR_PS_BITS_4TB; 72 73 /* 40 bits address */ 74 if ((max_addr & ADDR_MASK_36_TO_39) != 0U) 75 return TCR_PS_BITS_1TB; 76 77 /* 36 bits address */ 78 if ((max_addr & ADDR_MASK_32_TO_35) != 0U) 79 return TCR_PS_BITS_64GB; 80 81 return TCR_PS_BITS_4GB; 82 } 83 84 #if ENABLE_ASSERTIONS 85 /* 86 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 87 * supported in ARMv8.2 onwards. 88 */ 89 static const unsigned int pa_range_bits_arr[] = { 90 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 91 PARANGE_0101, PARANGE_0110 92 }; 93 94 unsigned long long xlat_arch_get_max_supported_pa(void) 95 { 96 u_register_t pa_range = read_id_aa64mmfr0_el1() & 97 ID_AA64MMFR0_EL1_PARANGE_MASK; 98 99 /* All other values are reserved */ 100 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 101 102 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 103 } 104 #endif /* ENABLE_ASSERTIONS*/ 105 106 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 107 { 108 if (ctx->xlat_regime == EL1_EL0_REGIME) { 109 assert(xlat_arch_current_el() >= 1U); 110 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; 111 } else if (ctx->xlat_regime == EL2_REGIME) { 112 assert(xlat_arch_current_el() >= 2U); 113 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; 114 } else { 115 assert(ctx->xlat_regime == EL3_REGIME); 116 assert(xlat_arch_current_el() >= 3U); 117 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; 118 } 119 } 120 121 bool is_dcache_enabled(void) 122 { 123 unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); 124 125 if (el == 1U) { 126 return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; 127 } else if (el == 2U) { 128 return (read_sctlr_el2() & SCTLR_C_BIT) != 0U; 129 } else { 130 return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; 131 } 132 } 133 134 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 135 { 136 if (xlat_regime == EL1_EL0_REGIME) { 137 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); 138 } else { 139 assert((xlat_regime == EL2_REGIME) || 140 (xlat_regime == EL3_REGIME)); 141 return UPPER_ATTRS(XN); 142 } 143 } 144 145 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 146 { 147 /* 148 * Ensure the translation table write has drained into memory before 149 * invalidating the TLB entry. 150 */ 151 dsbishst(); 152 153 /* 154 * This function only supports invalidation of TLB entries for the EL3 155 * and EL1&0 translation regimes. 156 * 157 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 158 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 159 */ 160 if (xlat_regime == EL1_EL0_REGIME) { 161 assert(xlat_arch_current_el() >= 1U); 162 tlbivaae1is(TLBI_ADDR(va)); 163 } else if (xlat_regime == EL2_REGIME) { 164 assert(xlat_arch_current_el() >= 2U); 165 tlbivae2is(TLBI_ADDR(va)); 166 } else { 167 assert(xlat_regime == EL3_REGIME); 168 assert(xlat_arch_current_el() >= 3U); 169 tlbivae3is(TLBI_ADDR(va)); 170 } 171 } 172 173 void xlat_arch_tlbi_va_sync(void) 174 { 175 /* 176 * A TLB maintenance instruction can complete at any time after 177 * it is issued, but is only guaranteed to be complete after the 178 * execution of DSB by the PE that executed the TLB maintenance 179 * instruction. After the TLB invalidate instruction is 180 * complete, no new memory accesses using the invalidated TLB 181 * entries will be observed by any observer of the system 182 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 183 * "Ordering and completion of TLB maintenance instructions". 184 */ 185 dsbish(); 186 187 /* 188 * The effects of a completed TLB maintenance instruction are 189 * only guaranteed to be visible on the PE that executed the 190 * instruction after the execution of an ISB instruction by the 191 * PE that executed the TLB maintenance instruction. 192 */ 193 isb(); 194 } 195 196 unsigned int xlat_arch_current_el(void) 197 { 198 unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); 199 200 assert(el > 0U); 201 202 return el; 203 } 204 205 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 206 const uint64_t *base_table, unsigned long long max_pa, 207 uintptr_t max_va, int xlat_regime) 208 { 209 uint64_t mair, ttbr0, tcr; 210 uintptr_t virtual_addr_space_size; 211 212 /* Set attributes in the right indices of the MAIR. */ 213 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 214 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 215 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 216 217 /* 218 * Limit the input address ranges and memory region sizes translated 219 * using TTBR0 to the given virtual address space size. 220 */ 221 assert(max_va < ((uint64_t)UINTPTR_MAX)); 222 223 virtual_addr_space_size = (uintptr_t)max_va + 1U; 224 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 225 226 /* 227 * __builtin_ctzll(0) is undefined but here we are guaranteed that 228 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 229 */ 230 int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); 231 232 tcr = (uint64_t) t0sz; 233 234 /* 235 * Set the cacheability and shareability attributes for memory 236 * associated with translation table walks. 237 */ 238 if ((flags & XLAT_TABLE_NC) != 0U) { 239 /* Inner & outer non-cacheable non-shareable. */ 240 tcr |= TCR_SH_NON_SHAREABLE | 241 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 242 } else { 243 /* Inner & outer WBWA & shareable. */ 244 tcr |= TCR_SH_INNER_SHAREABLE | 245 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 246 } 247 248 /* 249 * It is safer to restrict the max physical address accessible by the 250 * hardware as much as possible. 251 */ 252 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 253 254 if (xlat_regime == EL1_EL0_REGIME) { 255 /* 256 * TCR_EL1.EPD1: Disable translation table walk for addresses 257 * that are translated using TTBR1_EL1. 258 */ 259 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 260 } else if (xlat_regime == EL2_REGIME) { 261 tcr |= TCR_EL2_RES1 | (tcr_ps_bits << TCR_EL2_PS_SHIFT); 262 } else { 263 assert(xlat_regime == EL3_REGIME); 264 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 265 } 266 267 /* Set TTBR bits as well */ 268 ttbr0 = (uint64_t) base_table; 269 270 if (is_armv8_2_ttcnp_present()) { 271 /* Enable CnP bit so as to share page tables with all PEs. */ 272 ttbr0 |= TTBR_CNP_BIT; 273 } 274 275 params[MMU_CFG_MAIR] = mair; 276 params[MMU_CFG_TCR] = tcr; 277 params[MMU_CFG_TTBR0] = ttbr0; 278 } 279