1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <sys/types.h> 12 #include <utils_def.h> 13 #include <xlat_tables_v2.h> 14 #include "../xlat_tables_private.h" 15 16 uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; 17 18 /* 19 * Returns 1 if the provided granule size is supported, 0 otherwise. 20 */ 21 int xlat_arch_is_granule_size_supported(size_t size) 22 { 23 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 24 25 if (size == (4U * 1024U)) { 26 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 27 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 28 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 29 } else if (size == (16U * 1024U)) { 30 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 31 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 32 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 33 } else if (size == (64U * 1024U)) { 34 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 35 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 36 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 37 } 38 39 return 0; 40 } 41 42 size_t xlat_arch_get_max_supported_granule_size(void) 43 { 44 if (xlat_arch_is_granule_size_supported(64U * 1024U)) { 45 return 64U * 1024U; 46 } else if (xlat_arch_is_granule_size_supported(16U * 1024U)) { 47 return 16U * 1024U; 48 } else { 49 assert(xlat_arch_is_granule_size_supported(4U * 1024U)); 50 return 4U * 1024U; 51 } 52 } 53 54 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 55 { 56 /* Physical address can't exceed 48 bits */ 57 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 58 59 /* 48 bits address */ 60 if (max_addr & ADDR_MASK_44_TO_47) 61 return TCR_PS_BITS_256TB; 62 63 /* 44 bits address */ 64 if (max_addr & ADDR_MASK_42_TO_43) 65 return TCR_PS_BITS_16TB; 66 67 /* 42 bits address */ 68 if (max_addr & ADDR_MASK_40_TO_41) 69 return TCR_PS_BITS_4TB; 70 71 /* 40 bits address */ 72 if (max_addr & ADDR_MASK_36_TO_39) 73 return TCR_PS_BITS_1TB; 74 75 /* 36 bits address */ 76 if (max_addr & ADDR_MASK_32_TO_35) 77 return TCR_PS_BITS_64GB; 78 79 return TCR_PS_BITS_4GB; 80 } 81 82 #if ENABLE_ASSERTIONS 83 /* 84 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 85 * supported in ARMv8.2 onwards. 86 */ 87 static const unsigned int pa_range_bits_arr[] = { 88 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 89 PARANGE_0101, PARANGE_0110 90 }; 91 92 unsigned long long xlat_arch_get_max_supported_pa(void) 93 { 94 u_register_t pa_range = read_id_aa64mmfr0_el1() & 95 ID_AA64MMFR0_EL1_PARANGE_MASK; 96 97 /* All other values are reserved */ 98 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 99 100 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 101 } 102 #endif /* ENABLE_ASSERTIONS*/ 103 104 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 105 { 106 if (ctx->xlat_regime == EL1_EL0_REGIME) { 107 assert(xlat_arch_current_el() >= 1); 108 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 109 } else { 110 assert(ctx->xlat_regime == EL3_REGIME); 111 assert(xlat_arch_current_el() >= 3); 112 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 113 } 114 } 115 116 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 117 { 118 if (xlat_regime == EL1_EL0_REGIME) { 119 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); 120 } else { 121 assert(xlat_regime == EL3_REGIME); 122 return UPPER_ATTRS(XN); 123 } 124 } 125 126 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 127 { 128 /* 129 * Ensure the translation table write has drained into memory before 130 * invalidating the TLB entry. 131 */ 132 dsbishst(); 133 134 /* 135 * This function only supports invalidation of TLB entries for the EL3 136 * and EL1&0 translation regimes. 137 * 138 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 139 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 140 */ 141 if (xlat_regime == EL1_EL0_REGIME) { 142 assert(xlat_arch_current_el() >= 1); 143 tlbivaae1is(TLBI_ADDR(va)); 144 } else { 145 assert(xlat_regime == EL3_REGIME); 146 assert(xlat_arch_current_el() >= 3); 147 tlbivae3is(TLBI_ADDR(va)); 148 } 149 } 150 151 void xlat_arch_tlbi_va_sync(void) 152 { 153 /* 154 * A TLB maintenance instruction can complete at any time after 155 * it is issued, but is only guaranteed to be complete after the 156 * execution of DSB by the PE that executed the TLB maintenance 157 * instruction. After the TLB invalidate instruction is 158 * complete, no new memory accesses using the invalidated TLB 159 * entries will be observed by any observer of the system 160 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 161 * "Ordering and completion of TLB maintenance instructions". 162 */ 163 dsbish(); 164 165 /* 166 * The effects of a completed TLB maintenance instruction are 167 * only guaranteed to be visible on the PE that executed the 168 * instruction after the execution of an ISB instruction by the 169 * PE that executed the TLB maintenance instruction. 170 */ 171 isb(); 172 } 173 174 int xlat_arch_current_el(void) 175 { 176 int el = GET_EL(read_CurrentEl()); 177 178 assert(el > 0); 179 180 return el; 181 } 182 183 void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table, 184 unsigned long long max_pa, uintptr_t max_va, int xlat_regime) 185 { 186 uint64_t mair, ttbr, tcr; 187 uintptr_t virtual_addr_space_size; 188 189 /* Set attributes in the right indices of the MAIR. */ 190 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 191 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 192 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 193 194 ttbr = (uint64_t) base_table; 195 196 /* 197 * Limit the input address ranges and memory region sizes translated 198 * using TTBR0 to the given virtual address space size. 199 */ 200 assert(max_va < ((uint64_t) UINTPTR_MAX)); 201 202 virtual_addr_space_size = max_va + 1; 203 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 204 205 /* 206 * __builtin_ctzll(0) is undefined but here we are guaranteed that 207 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 208 */ 209 tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); 210 211 /* 212 * Set the cacheability and shareability attributes for memory 213 * associated with translation table walks. 214 */ 215 if ((flags & XLAT_TABLE_NC) != 0) { 216 /* Inner & outer non-cacheable non-shareable. */ 217 tcr |= TCR_SH_NON_SHAREABLE | 218 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 219 } else { 220 /* Inner & outer WBWA & shareable. */ 221 tcr |= TCR_SH_INNER_SHAREABLE | 222 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 223 } 224 225 /* 226 * It is safer to restrict the max physical address accessible by the 227 * hardware as much as possible. 228 */ 229 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 230 231 if (xlat_regime == EL1_EL0_REGIME) { 232 /* 233 * TCR_EL1.EPD1: Disable translation table walk for addresses 234 * that are translated using TTBR1_EL1. 235 */ 236 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 237 } else { 238 assert(xlat_regime == EL3_REGIME); 239 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 240 } 241 242 mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair; 243 mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr; 244 245 /* Set TTBR bits as well */ 246 if (ARM_ARCH_AT_LEAST(8, 2)) { 247 /* 248 * Enable CnP bit so as to share page tables with all PEs. This 249 * is mandatory for ARMv8.2 implementations. 250 */ 251 ttbr |= TTBR_CNP_BIT; 252 } 253 254 mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr; 255 mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32); 256 } 257