1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 20 { 21 /* Physical address can't exceed 48 bits */ 22 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 23 24 /* 48 bits address */ 25 if (max_addr & ADDR_MASK_44_TO_47) 26 return TCR_PS_BITS_256TB; 27 28 /* 44 bits address */ 29 if (max_addr & ADDR_MASK_42_TO_43) 30 return TCR_PS_BITS_16TB; 31 32 /* 42 bits address */ 33 if (max_addr & ADDR_MASK_40_TO_41) 34 return TCR_PS_BITS_4TB; 35 36 /* 40 bits address */ 37 if (max_addr & ADDR_MASK_36_TO_39) 38 return TCR_PS_BITS_1TB; 39 40 /* 36 bits address */ 41 if (max_addr & ADDR_MASK_32_TO_35) 42 return TCR_PS_BITS_64GB; 43 44 return TCR_PS_BITS_4GB; 45 } 46 47 #if ENABLE_ASSERTIONS 48 /* Physical Address ranges supported in the AArch64 Memory Model */ 49 static const unsigned int pa_range_bits_arr[] = { 50 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 51 PARANGE_0101 52 }; 53 54 unsigned long long xlat_arch_get_max_supported_pa(void) 55 { 56 u_register_t pa_range = read_id_aa64mmfr0_el1() & 57 ID_AA64MMFR0_EL1_PARANGE_MASK; 58 59 /* All other values are reserved */ 60 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 61 62 return (1ull << pa_range_bits_arr[pa_range]) - 1ull; 63 } 64 #endif /* ENABLE_ASSERTIONS*/ 65 66 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 67 { 68 if (ctx->xlat_regime == EL1_EL0_REGIME) { 69 assert(xlat_arch_current_el() >= 1); 70 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 71 } else { 72 assert(ctx->xlat_regime == EL3_REGIME); 73 assert(xlat_arch_current_el() >= 3); 74 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 75 } 76 } 77 78 79 void xlat_arch_tlbi_va(uintptr_t va) 80 { 81 #if IMAGE_EL == 1 82 assert(IS_IN_EL(1)); 83 xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); 84 #elif IMAGE_EL == 3 85 assert(IS_IN_EL(3)); 86 xlat_arch_tlbi_va_regime(va, EL3_REGIME); 87 #endif 88 } 89 90 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime) 91 { 92 /* 93 * Ensure the translation table write has drained into memory before 94 * invalidating the TLB entry. 95 */ 96 dsbishst(); 97 98 /* 99 * This function only supports invalidation of TLB entries for the EL3 100 * and EL1&0 translation regimes. 101 * 102 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 103 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 104 */ 105 if (xlat_regime == EL1_EL0_REGIME) { 106 assert(xlat_arch_current_el() >= 1); 107 tlbivaae1is(TLBI_ADDR(va)); 108 } else { 109 assert(xlat_regime == EL3_REGIME); 110 assert(xlat_arch_current_el() >= 3); 111 tlbivae3is(TLBI_ADDR(va)); 112 } 113 } 114 115 void xlat_arch_tlbi_va_sync(void) 116 { 117 /* 118 * A TLB maintenance instruction can complete at any time after 119 * it is issued, but is only guaranteed to be complete after the 120 * execution of DSB by the PE that executed the TLB maintenance 121 * instruction. After the TLB invalidate instruction is 122 * complete, no new memory accesses using the invalidated TLB 123 * entries will be observed by any observer of the system 124 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 125 * "Ordering and completion of TLB maintenance instructions". 126 */ 127 dsbish(); 128 129 /* 130 * The effects of a completed TLB maintenance instruction are 131 * only guaranteed to be visible on the PE that executed the 132 * instruction after the execution of an ISB instruction by the 133 * PE that executed the TLB maintenance instruction. 134 */ 135 isb(); 136 } 137 138 int xlat_arch_current_el(void) 139 { 140 int el = GET_EL(read_CurrentEl()); 141 142 assert(el > 0); 143 144 return el; 145 } 146 147 /******************************************************************************* 148 * Macro generating the code for the function enabling the MMU in the given 149 * exception level, assuming that the pagetables have already been created. 150 * 151 * _el: Exception level at which the function will run 152 * _tlbi_fct: Function to invalidate the TLBs at the current 153 * exception level 154 ******************************************************************************/ 155 #define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ 156 static void enable_mmu_internal_el##_el(int flags, \ 157 uint64_t mair, \ 158 uint64_t tcr, \ 159 uint64_t ttbr) \ 160 { \ 161 uint32_t sctlr = read_sctlr_el##_el(); \ 162 assert((sctlr & SCTLR_M_BIT) == 0); \ 163 \ 164 /* Invalidate TLBs at the current exception level */ \ 165 _tlbi_fct(); \ 166 \ 167 write_mair_el##_el(mair); \ 168 write_tcr_el##_el(tcr); \ 169 \ 170 /* Set TTBR bits as well */ \ 171 if (ARM_ARCH_AT_LEAST(8, 2)) { \ 172 /* Enable CnP bit so as to share page tables */ \ 173 /* with all PEs. This is mandatory for */ \ 174 /* ARMv8.2 implementations. */ \ 175 ttbr |= TTBR_CNP_BIT; \ 176 } \ 177 write_ttbr0_el##_el(ttbr); \ 178 \ 179 /* Ensure all translation table writes have drained */ \ 180 /* into memory, the TLB invalidation is complete, */ \ 181 /* and translation register writes are committed */ \ 182 /* before enabling the MMU */ \ 183 dsbish(); \ 184 isb(); \ 185 \ 186 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 187 if (flags & DISABLE_DCACHE) \ 188 sctlr &= ~SCTLR_C_BIT; \ 189 else \ 190 sctlr |= SCTLR_C_BIT; \ 191 \ 192 write_sctlr_el##_el(sctlr); \ 193 \ 194 /* Ensure the MMU enable takes effect immediately */ \ 195 isb(); \ 196 } 197 198 /* Define EL1 and EL3 variants of the function enabling the MMU */ 199 #if IMAGE_EL == 1 200 DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) 201 #elif IMAGE_EL == 3 202 DEFINE_ENABLE_MMU_EL(3, tlbialle3) 203 #endif 204 205 void enable_mmu_arch(unsigned int flags, 206 uint64_t *base_table, 207 unsigned long long max_pa, 208 uintptr_t max_va) 209 { 210 uint64_t mair, ttbr, tcr; 211 212 /* Set attributes in the right indices of the MAIR. */ 213 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 214 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 215 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 216 217 ttbr = (uint64_t) base_table; 218 219 /* 220 * Set TCR bits as well. 221 */ 222 223 /* 224 * Limit the input address ranges and memory region sizes translated 225 * using TTBR0 to the given virtual address space size. 226 */ 227 assert(max_va < UINTPTR_MAX); 228 uintptr_t virtual_addr_space_size = max_va + 1; 229 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 230 /* 231 * __builtin_ctzll(0) is undefined but here we are guaranteed that 232 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 233 */ 234 tcr = 64 - __builtin_ctzll(virtual_addr_space_size); 235 236 /* 237 * Set the cacheability and shareability attributes for memory 238 * associated with translation table walks. 239 */ 240 if (flags & XLAT_TABLE_NC) { 241 /* Inner & outer non-cacheable non-shareable. */ 242 tcr |= TCR_SH_NON_SHAREABLE | 243 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 244 } else { 245 /* Inner & outer WBWA & shareable. */ 246 tcr |= TCR_SH_INNER_SHAREABLE | 247 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 248 } 249 250 /* 251 * It is safer to restrict the max physical address accessible by the 252 * hardware as much as possible. 253 */ 254 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 255 256 #if IMAGE_EL == 1 257 assert(IS_IN_EL(1)); 258 /* 259 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 260 * translated using TTBR1_EL1. 261 */ 262 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 263 enable_mmu_internal_el1(flags, mair, tcr, ttbr); 264 #elif IMAGE_EL == 3 265 assert(IS_IN_EL(3)); 266 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 267 enable_mmu_internal_el3(flags, mair, tcr, ttbr); 268 #endif 269 } 270