1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <stdbool.h> 12 #include <sys/types.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 /* 18 * Returns true if the provided granule size is supported, false otherwise. 19 */ 20 bool xlat_arch_is_granule_size_supported(size_t size) 21 { 22 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 23 24 if (size == PAGE_SIZE_4KB) { 25 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 26 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 27 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 28 } else if (size == PAGE_SIZE_16KB) { 29 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 30 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 31 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 32 } else if (size == PAGE_SIZE_64KB) { 33 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 34 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 35 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 36 } else { 37 return 0; 38 } 39 } 40 41 size_t xlat_arch_get_max_supported_granule_size(void) 42 { 43 if (xlat_arch_is_granule_size_supported(PAGE_SIZE_64KB)) { 44 return PAGE_SIZE_64KB; 45 } else if (xlat_arch_is_granule_size_supported(PAGE_SIZE_16KB)) { 46 return PAGE_SIZE_16KB; 47 } else { 48 assert(xlat_arch_is_granule_size_supported(PAGE_SIZE_4KB)); 49 return PAGE_SIZE_4KB; 50 } 51 } 52 53 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 54 { 55 /* Physical address can't exceed 48 bits */ 56 assert((max_addr & ADDR_MASK_48_TO_63) == 0U); 57 58 /* 48 bits address */ 59 if ((max_addr & ADDR_MASK_44_TO_47) != 0U) 60 return TCR_PS_BITS_256TB; 61 62 /* 44 bits address */ 63 if ((max_addr & ADDR_MASK_42_TO_43) != 0U) 64 return TCR_PS_BITS_16TB; 65 66 /* 42 bits address */ 67 if ((max_addr & ADDR_MASK_40_TO_41) != 0U) 68 return TCR_PS_BITS_4TB; 69 70 /* 40 bits address */ 71 if ((max_addr & ADDR_MASK_36_TO_39) != 0U) 72 return TCR_PS_BITS_1TB; 73 74 /* 36 bits address */ 75 if ((max_addr & ADDR_MASK_32_TO_35) != 0U) 76 return TCR_PS_BITS_64GB; 77 78 return TCR_PS_BITS_4GB; 79 } 80 81 #if ENABLE_ASSERTIONS 82 /* 83 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 84 * supported in ARMv8.2 onwards. 85 */ 86 static const unsigned int pa_range_bits_arr[] = { 87 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 88 PARANGE_0101, PARANGE_0110 89 }; 90 91 unsigned long long xlat_arch_get_max_supported_pa(void) 92 { 93 u_register_t pa_range = read_id_aa64mmfr0_el1() & 94 ID_AA64MMFR0_EL1_PARANGE_MASK; 95 96 /* All other values are reserved */ 97 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 98 99 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 100 } 101 #endif /* ENABLE_ASSERTIONS*/ 102 103 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 104 { 105 if (ctx->xlat_regime == EL1_EL0_REGIME) { 106 assert(xlat_arch_current_el() >= 1U); 107 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; 108 } else { 109 assert(ctx->xlat_regime == EL3_REGIME); 110 assert(xlat_arch_current_el() >= 3U); 111 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; 112 } 113 } 114 115 bool is_dcache_enabled(void) 116 { 117 unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); 118 119 if (el == 1U) { 120 return (read_sctlr_el1() & SCTLR_C_BIT) != 0U; 121 } else { 122 return (read_sctlr_el3() & SCTLR_C_BIT) != 0U; 123 } 124 } 125 126 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 127 { 128 if (xlat_regime == EL1_EL0_REGIME) { 129 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); 130 } else { 131 assert(xlat_regime == EL3_REGIME); 132 return UPPER_ATTRS(XN); 133 } 134 } 135 136 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 137 { 138 /* 139 * Ensure the translation table write has drained into memory before 140 * invalidating the TLB entry. 141 */ 142 dsbishst(); 143 144 /* 145 * This function only supports invalidation of TLB entries for the EL3 146 * and EL1&0 translation regimes. 147 * 148 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 149 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 150 */ 151 if (xlat_regime == EL1_EL0_REGIME) { 152 assert(xlat_arch_current_el() >= 1U); 153 tlbivaae1is(TLBI_ADDR(va)); 154 } else { 155 assert(xlat_regime == EL3_REGIME); 156 assert(xlat_arch_current_el() >= 3U); 157 tlbivae3is(TLBI_ADDR(va)); 158 } 159 } 160 161 void xlat_arch_tlbi_va_sync(void) 162 { 163 /* 164 * A TLB maintenance instruction can complete at any time after 165 * it is issued, but is only guaranteed to be complete after the 166 * execution of DSB by the PE that executed the TLB maintenance 167 * instruction. After the TLB invalidate instruction is 168 * complete, no new memory accesses using the invalidated TLB 169 * entries will be observed by any observer of the system 170 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 171 * "Ordering and completion of TLB maintenance instructions". 172 */ 173 dsbish(); 174 175 /* 176 * The effects of a completed TLB maintenance instruction are 177 * only guaranteed to be visible on the PE that executed the 178 * instruction after the execution of an ISB instruction by the 179 * PE that executed the TLB maintenance instruction. 180 */ 181 isb(); 182 } 183 184 unsigned int xlat_arch_current_el(void) 185 { 186 unsigned int el = (unsigned int)GET_EL(read_CurrentEl()); 187 188 assert(el > 0U); 189 190 return el; 191 } 192 193 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 194 const uint64_t *base_table, unsigned long long max_pa, 195 uintptr_t max_va, int xlat_regime) 196 { 197 uint64_t mair, ttbr0, tcr; 198 uintptr_t virtual_addr_space_size; 199 200 /* Set attributes in the right indices of the MAIR. */ 201 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 202 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 203 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 204 205 /* 206 * Limit the input address ranges and memory region sizes translated 207 * using TTBR0 to the given virtual address space size. 208 */ 209 assert(max_va < ((uint64_t)UINTPTR_MAX)); 210 211 virtual_addr_space_size = (uintptr_t)max_va + 1U; 212 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 213 214 /* 215 * __builtin_ctzll(0) is undefined but here we are guaranteed that 216 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 217 */ 218 int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); 219 220 tcr = (uint64_t) t0sz; 221 222 /* 223 * Set the cacheability and shareability attributes for memory 224 * associated with translation table walks. 225 */ 226 if ((flags & XLAT_TABLE_NC) != 0U) { 227 /* Inner & outer non-cacheable non-shareable. */ 228 tcr |= TCR_SH_NON_SHAREABLE | 229 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 230 } else { 231 /* Inner & outer WBWA & shareable. */ 232 tcr |= TCR_SH_INNER_SHAREABLE | 233 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 234 } 235 236 /* 237 * It is safer to restrict the max physical address accessible by the 238 * hardware as much as possible. 239 */ 240 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 241 242 if (xlat_regime == EL1_EL0_REGIME) { 243 /* 244 * TCR_EL1.EPD1: Disable translation table walk for addresses 245 * that are translated using TTBR1_EL1. 246 */ 247 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 248 } else { 249 assert(xlat_regime == EL3_REGIME); 250 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 251 } 252 253 /* Set TTBR bits as well */ 254 ttbr0 = (uint64_t) base_table; 255 256 #if ARM_ARCH_AT_LEAST(8, 2) 257 /* 258 * Enable CnP bit so as to share page tables with all PEs. This 259 * is mandatory for ARMv8.2 implementations. 260 */ 261 ttbr0 |= TTBR_CNP_BIT; 262 #endif 263 264 params[MMU_CFG_MAIR] = mair; 265 params[MMU_CFG_TCR] = tcr; 266 params[MMU_CFG_TTBR0] = ttbr0; 267 } 268