1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <sys/types.h> 12 #include <utils_def.h> 13 #include <xlat_tables_v2.h> 14 #include "../xlat_tables_private.h" 15 16 /* 17 * Returns 1 if the provided granule size is supported, 0 otherwise. 18 */ 19 int xlat_arch_is_granule_size_supported(size_t size) 20 { 21 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 22 23 if (size == (4U * 1024U)) { 24 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 25 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 26 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 27 } else if (size == (16U * 1024U)) { 28 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 29 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 30 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 31 } else if (size == (64U * 1024U)) { 32 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 33 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 34 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 35 } 36 37 return 0; 38 } 39 40 size_t xlat_arch_get_max_supported_granule_size(void) 41 { 42 if (xlat_arch_is_granule_size_supported(64U * 1024U)) { 43 return 64U * 1024U; 44 } else if (xlat_arch_is_granule_size_supported(16U * 1024U)) { 45 return 16U * 1024U; 46 } else { 47 assert(xlat_arch_is_granule_size_supported(4U * 1024U)); 48 return 4U * 1024U; 49 } 50 } 51 52 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 53 { 54 /* Physical address can't exceed 48 bits */ 55 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 56 57 /* 48 bits address */ 58 if (max_addr & ADDR_MASK_44_TO_47) 59 return TCR_PS_BITS_256TB; 60 61 /* 44 bits address */ 62 if (max_addr & ADDR_MASK_42_TO_43) 63 return TCR_PS_BITS_16TB; 64 65 /* 42 bits address */ 66 if (max_addr & ADDR_MASK_40_TO_41) 67 return TCR_PS_BITS_4TB; 68 69 /* 40 bits address */ 70 if (max_addr & ADDR_MASK_36_TO_39) 71 return TCR_PS_BITS_1TB; 72 73 /* 36 bits address */ 74 if (max_addr & ADDR_MASK_32_TO_35) 75 return TCR_PS_BITS_64GB; 76 77 return TCR_PS_BITS_4GB; 78 } 79 80 #if ENABLE_ASSERTIONS 81 /* 82 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 83 * supported in ARMv8.2 onwards. 84 */ 85 static const unsigned int pa_range_bits_arr[] = { 86 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 87 PARANGE_0101, PARANGE_0110 88 }; 89 90 unsigned long long xlat_arch_get_max_supported_pa(void) 91 { 92 u_register_t pa_range = read_id_aa64mmfr0_el1() & 93 ID_AA64MMFR0_EL1_PARANGE_MASK; 94 95 /* All other values are reserved */ 96 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 97 98 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 99 } 100 #endif /* ENABLE_ASSERTIONS*/ 101 102 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 103 { 104 if (ctx->xlat_regime == EL1_EL0_REGIME) { 105 assert(xlat_arch_current_el() >= 1); 106 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 107 } else { 108 assert(ctx->xlat_regime == EL3_REGIME); 109 assert(xlat_arch_current_el() >= 3); 110 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 111 } 112 } 113 114 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 115 { 116 if (xlat_regime == EL1_EL0_REGIME) { 117 return UPPER_ATTRS(UXN) | UPPER_ATTRS(PXN); 118 } else { 119 assert(xlat_regime == EL3_REGIME); 120 return UPPER_ATTRS(XN); 121 } 122 } 123 124 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 125 { 126 /* 127 * Ensure the translation table write has drained into memory before 128 * invalidating the TLB entry. 129 */ 130 dsbishst(); 131 132 /* 133 * This function only supports invalidation of TLB entries for the EL3 134 * and EL1&0 translation regimes. 135 * 136 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 137 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 138 */ 139 if (xlat_regime == EL1_EL0_REGIME) { 140 assert(xlat_arch_current_el() >= 1); 141 tlbivaae1is(TLBI_ADDR(va)); 142 } else { 143 assert(xlat_regime == EL3_REGIME); 144 assert(xlat_arch_current_el() >= 3); 145 tlbivae3is(TLBI_ADDR(va)); 146 } 147 } 148 149 void xlat_arch_tlbi_va_sync(void) 150 { 151 /* 152 * A TLB maintenance instruction can complete at any time after 153 * it is issued, but is only guaranteed to be complete after the 154 * execution of DSB by the PE that executed the TLB maintenance 155 * instruction. After the TLB invalidate instruction is 156 * complete, no new memory accesses using the invalidated TLB 157 * entries will be observed by any observer of the system 158 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 159 * "Ordering and completion of TLB maintenance instructions". 160 */ 161 dsbish(); 162 163 /* 164 * The effects of a completed TLB maintenance instruction are 165 * only guaranteed to be visible on the PE that executed the 166 * instruction after the execution of an ISB instruction by the 167 * PE that executed the TLB maintenance instruction. 168 */ 169 isb(); 170 } 171 172 int xlat_arch_current_el(void) 173 { 174 int el = GET_EL(read_CurrentEl()); 175 176 assert(el > 0); 177 178 return el; 179 } 180 181 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 182 const uint64_t *base_table, unsigned long long max_pa, 183 uintptr_t max_va, int xlat_regime) 184 { 185 uint64_t mair, ttbr0, tcr; 186 uintptr_t virtual_addr_space_size; 187 188 /* Set attributes in the right indices of the MAIR. */ 189 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 190 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 191 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 192 193 /* 194 * Limit the input address ranges and memory region sizes translated 195 * using TTBR0 to the given virtual address space size. 196 */ 197 assert(max_va < ((uint64_t) UINTPTR_MAX)); 198 199 virtual_addr_space_size = max_va + 1; 200 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 201 202 /* 203 * __builtin_ctzll(0) is undefined but here we are guaranteed that 204 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 205 */ 206 tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); 207 208 /* 209 * Set the cacheability and shareability attributes for memory 210 * associated with translation table walks. 211 */ 212 if ((flags & XLAT_TABLE_NC) != 0) { 213 /* Inner & outer non-cacheable non-shareable. */ 214 tcr |= TCR_SH_NON_SHAREABLE | 215 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 216 } else { 217 /* Inner & outer WBWA & shareable. */ 218 tcr |= TCR_SH_INNER_SHAREABLE | 219 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 220 } 221 222 /* 223 * It is safer to restrict the max physical address accessible by the 224 * hardware as much as possible. 225 */ 226 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 227 228 if (xlat_regime == EL1_EL0_REGIME) { 229 /* 230 * TCR_EL1.EPD1: Disable translation table walk for addresses 231 * that are translated using TTBR1_EL1. 232 */ 233 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 234 } else { 235 assert(xlat_regime == EL3_REGIME); 236 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 237 } 238 239 /* Set TTBR bits as well */ 240 ttbr0 = (uint64_t) base_table; 241 242 #if ARM_ARCH_AT_LEAST(8, 2) 243 /* 244 * Enable CnP bit so as to share page tables with all PEs. This 245 * is mandatory for ARMv8.2 implementations. 246 */ 247 ttbr0 |= TTBR_CNP_BIT; 248 #endif 249 250 params[MMU_CFG_MAIR] = mair; 251 params[MMU_CFG_TCR] = tcr; 252 params[MMU_CFG_TTBR0] = ttbr0; 253 } 254