10cc7aa89SJeenu Viswambharan/* 20cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 30cc7aa89SJeenu Viswambharan * 40cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 50cc7aa89SJeenu Viswambharan */ 60cc7aa89SJeenu Viswambharan 70cc7aa89SJeenu Viswambharan#include <asm_macros.S> 80cc7aa89SJeenu Viswambharan#include <assert_macros.S> 90cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 100cc7aa89SJeenu Viswambharan 110cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el1 120cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el3 130cc7aa89SJeenu Viswambharan 140cc7aa89SJeenu Viswambharan /* Macros to read and write to system register for a given EL. */ 150cc7aa89SJeenu Viswambharan .macro _msr reg_name, el, gp_reg 160cc7aa89SJeenu Viswambharan msr \reg_name\()_el\()\el, \gp_reg 170cc7aa89SJeenu Viswambharan .endm 180cc7aa89SJeenu Viswambharan 190cc7aa89SJeenu Viswambharan .macro _mrs gp_reg, reg_name, el 200cc7aa89SJeenu Viswambharan mrs \gp_reg, \reg_name\()_el\()\el 210cc7aa89SJeenu Viswambharan .endm 220cc7aa89SJeenu Viswambharan 230cc7aa89SJeenu Viswambharan .macro define_mmu_enable_func el 240cc7aa89SJeenu Viswambharan func enable_mmu_direct_\()el\el 250cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 260cc7aa89SJeenu Viswambharan _mrs x1, sctlr, \el 270cc7aa89SJeenu Viswambharan tst x1, #SCTLR_M_BIT 280cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 290cc7aa89SJeenu Viswambharan#endif 300cc7aa89SJeenu Viswambharan 310cc7aa89SJeenu Viswambharan /* Invalidate TLB entries */ 320cc7aa89SJeenu Viswambharan .if \el == 1 330cc7aa89SJeenu Viswambharan TLB_INVALIDATE(vmalle1) 340cc7aa89SJeenu Viswambharan .else 350cc7aa89SJeenu Viswambharan .if \el == 3 360cc7aa89SJeenu Viswambharan TLB_INVALIDATE(alle3) 370cc7aa89SJeenu Viswambharan .else 380cc7aa89SJeenu Viswambharan .error "EL must be 1 or 3" 390cc7aa89SJeenu Viswambharan .endif 400cc7aa89SJeenu Viswambharan .endif 410cc7aa89SJeenu Viswambharan 420cc7aa89SJeenu Viswambharan mov x7, x0 430cc7aa89SJeenu Viswambharan ldr x0, =mmu_cfg_params 440cc7aa89SJeenu Viswambharan 450cc7aa89SJeenu Viswambharan /* MAIR */ 46*6563c0beSAntonio Nino Diaz ldr x1, [x0, #(MMU_CFG_MAIR << 3)] 470cc7aa89SJeenu Viswambharan _msr mair, \el, x1 480cc7aa89SJeenu Viswambharan 490cc7aa89SJeenu Viswambharan /* TCR */ 50*6563c0beSAntonio Nino Diaz ldr x2, [x0, #(MMU_CFG_TCR << 3)] 510cc7aa89SJeenu Viswambharan _msr tcr, \el, x2 520cc7aa89SJeenu Viswambharan 530cc7aa89SJeenu Viswambharan /* TTBR */ 54*6563c0beSAntonio Nino Diaz ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)] 550cc7aa89SJeenu Viswambharan _msr ttbr0, \el, x3 560cc7aa89SJeenu Viswambharan 570cc7aa89SJeenu Viswambharan /* 580cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 590cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 600cc7aa89SJeenu Viswambharan * committed before enabling the MMU 610cc7aa89SJeenu Viswambharan */ 620cc7aa89SJeenu Viswambharan dsb ish 630cc7aa89SJeenu Viswambharan isb 640cc7aa89SJeenu Viswambharan 650cc7aa89SJeenu Viswambharan /* Set and clear required fields of SCTLR */ 660cc7aa89SJeenu Viswambharan _mrs x4, sctlr, \el 670cc7aa89SJeenu Viswambharan mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 680cc7aa89SJeenu Viswambharan orr x4, x4, x5 690cc7aa89SJeenu Viswambharan 700cc7aa89SJeenu Viswambharan /* Additionally, amend SCTLR fields based on flags */ 710cc7aa89SJeenu Viswambharan bic x5, x4, #SCTLR_C_BIT 720cc7aa89SJeenu Viswambharan tst x7, #DISABLE_DCACHE 730cc7aa89SJeenu Viswambharan csel x4, x5, x4, ne 740cc7aa89SJeenu Viswambharan 750cc7aa89SJeenu Viswambharan _msr sctlr, \el, x4 760cc7aa89SJeenu Viswambharan isb 770cc7aa89SJeenu Viswambharan 780cc7aa89SJeenu Viswambharan ret 790cc7aa89SJeenu Viswambharan endfunc enable_mmu_direct_\()el\el 800cc7aa89SJeenu Viswambharan .endm 810cc7aa89SJeenu Viswambharan 820cc7aa89SJeenu Viswambharan /* 830cc7aa89SJeenu Viswambharan * Define MMU-enabling functions for EL1 and EL3: 840cc7aa89SJeenu Viswambharan * 850cc7aa89SJeenu Viswambharan * enable_mmu_direct_el1 860cc7aa89SJeenu Viswambharan * enable_mmu_direct_el3 870cc7aa89SJeenu Viswambharan */ 880cc7aa89SJeenu Viswambharan define_mmu_enable_func 1 890cc7aa89SJeenu Viswambharan define_mmu_enable_func 3 90