10cc7aa89SJeenu Viswambharan/* 20cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 30cc7aa89SJeenu Viswambharan * 40cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 50cc7aa89SJeenu Viswambharan */ 60cc7aa89SJeenu Viswambharan 70cc7aa89SJeenu Viswambharan#include <asm_macros.S> 80cc7aa89SJeenu Viswambharan#include <assert_macros.S> 90cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 100cc7aa89SJeenu Viswambharan 110cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el1 12*1a92a0e0SAntonio Nino Diaz .global enable_mmu_direct_el2 130cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el3 140cc7aa89SJeenu Viswambharan 150cc7aa89SJeenu Viswambharan /* Macros to read and write to system register for a given EL. */ 160cc7aa89SJeenu Viswambharan .macro _msr reg_name, el, gp_reg 170cc7aa89SJeenu Viswambharan msr \reg_name\()_el\()\el, \gp_reg 180cc7aa89SJeenu Viswambharan .endm 190cc7aa89SJeenu Viswambharan 200cc7aa89SJeenu Viswambharan .macro _mrs gp_reg, reg_name, el 210cc7aa89SJeenu Viswambharan mrs \gp_reg, \reg_name\()_el\()\el 220cc7aa89SJeenu Viswambharan .endm 230cc7aa89SJeenu Viswambharan 24*1a92a0e0SAntonio Nino Diaz .macro tlbi_invalidate_all el 25*1a92a0e0SAntonio Nino Diaz .if \el == 1 26*1a92a0e0SAntonio Nino Diaz TLB_INVALIDATE(vmalle1) 27*1a92a0e0SAntonio Nino Diaz .elseif \el == 2 28*1a92a0e0SAntonio Nino Diaz TLB_INVALIDATE(alle2) 29*1a92a0e0SAntonio Nino Diaz .elseif \el == 3 30*1a92a0e0SAntonio Nino Diaz TLB_INVALIDATE(alle3) 31*1a92a0e0SAntonio Nino Diaz .else 32*1a92a0e0SAntonio Nino Diaz .error "EL must be 1, 2 or 3" 33*1a92a0e0SAntonio Nino Diaz .endif 34*1a92a0e0SAntonio Nino Diaz .endm 35*1a92a0e0SAntonio Nino Diaz 36*1a92a0e0SAntonio Nino Diaz /* void enable_mmu_direct_el<x>(unsigned int flags) */ 370cc7aa89SJeenu Viswambharan .macro define_mmu_enable_func el 380cc7aa89SJeenu Viswambharan func enable_mmu_direct_\()el\el 390cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 400cc7aa89SJeenu Viswambharan _mrs x1, sctlr, \el 410cc7aa89SJeenu Viswambharan tst x1, #SCTLR_M_BIT 420cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 430cc7aa89SJeenu Viswambharan#endif 44*1a92a0e0SAntonio Nino Diaz /* Invalidate all TLB entries */ 45*1a92a0e0SAntonio Nino Diaz tlbi_invalidate_all \el 460cc7aa89SJeenu Viswambharan 470cc7aa89SJeenu Viswambharan mov x7, x0 480cc7aa89SJeenu Viswambharan ldr x0, =mmu_cfg_params 490cc7aa89SJeenu Viswambharan 500cc7aa89SJeenu Viswambharan /* MAIR */ 516563c0beSAntonio Nino Diaz ldr x1, [x0, #(MMU_CFG_MAIR << 3)] 520cc7aa89SJeenu Viswambharan _msr mair, \el, x1 530cc7aa89SJeenu Viswambharan 540cc7aa89SJeenu Viswambharan /* TCR */ 556563c0beSAntonio Nino Diaz ldr x2, [x0, #(MMU_CFG_TCR << 3)] 560cc7aa89SJeenu Viswambharan _msr tcr, \el, x2 570cc7aa89SJeenu Viswambharan 580cc7aa89SJeenu Viswambharan /* TTBR */ 596563c0beSAntonio Nino Diaz ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)] 600cc7aa89SJeenu Viswambharan _msr ttbr0, \el, x3 610cc7aa89SJeenu Viswambharan 620cc7aa89SJeenu Viswambharan /* 630cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 640cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 650cc7aa89SJeenu Viswambharan * committed before enabling the MMU 660cc7aa89SJeenu Viswambharan */ 670cc7aa89SJeenu Viswambharan dsb ish 680cc7aa89SJeenu Viswambharan isb 690cc7aa89SJeenu Viswambharan 700cc7aa89SJeenu Viswambharan /* Set and clear required fields of SCTLR */ 710cc7aa89SJeenu Viswambharan _mrs x4, sctlr, \el 720cc7aa89SJeenu Viswambharan mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 730cc7aa89SJeenu Viswambharan orr x4, x4, x5 740cc7aa89SJeenu Viswambharan 750cc7aa89SJeenu Viswambharan /* Additionally, amend SCTLR fields based on flags */ 760cc7aa89SJeenu Viswambharan bic x5, x4, #SCTLR_C_BIT 770cc7aa89SJeenu Viswambharan tst x7, #DISABLE_DCACHE 780cc7aa89SJeenu Viswambharan csel x4, x5, x4, ne 790cc7aa89SJeenu Viswambharan 800cc7aa89SJeenu Viswambharan _msr sctlr, \el, x4 810cc7aa89SJeenu Viswambharan isb 820cc7aa89SJeenu Viswambharan 830cc7aa89SJeenu Viswambharan ret 840cc7aa89SJeenu Viswambharan endfunc enable_mmu_direct_\()el\el 850cc7aa89SJeenu Viswambharan .endm 860cc7aa89SJeenu Viswambharan 870cc7aa89SJeenu Viswambharan /* 880cc7aa89SJeenu Viswambharan * Define MMU-enabling functions for EL1 and EL3: 890cc7aa89SJeenu Viswambharan * 900cc7aa89SJeenu Viswambharan * enable_mmu_direct_el1 910cc7aa89SJeenu Viswambharan * enable_mmu_direct_el3 920cc7aa89SJeenu Viswambharan */ 930cc7aa89SJeenu Viswambharan define_mmu_enable_func 1 94*1a92a0e0SAntonio Nino Diaz define_mmu_enable_func 2 950cc7aa89SJeenu Viswambharan define_mmu_enable_func 3 96