1*0cc7aa89SJeenu Viswambharan/* 2*0cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*0cc7aa89SJeenu Viswambharan * 4*0cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 5*0cc7aa89SJeenu Viswambharan */ 6*0cc7aa89SJeenu Viswambharan 7*0cc7aa89SJeenu Viswambharan#include <asm_macros.S> 8*0cc7aa89SJeenu Viswambharan#include <assert_macros.S> 9*0cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 10*0cc7aa89SJeenu Viswambharan 11*0cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el1 12*0cc7aa89SJeenu Viswambharan .global enable_mmu_direct_el3 13*0cc7aa89SJeenu Viswambharan 14*0cc7aa89SJeenu Viswambharan /* Macros to read and write to system register for a given EL. */ 15*0cc7aa89SJeenu Viswambharan .macro _msr reg_name, el, gp_reg 16*0cc7aa89SJeenu Viswambharan msr \reg_name\()_el\()\el, \gp_reg 17*0cc7aa89SJeenu Viswambharan .endm 18*0cc7aa89SJeenu Viswambharan 19*0cc7aa89SJeenu Viswambharan .macro _mrs gp_reg, reg_name, el 20*0cc7aa89SJeenu Viswambharan mrs \gp_reg, \reg_name\()_el\()\el 21*0cc7aa89SJeenu Viswambharan .endm 22*0cc7aa89SJeenu Viswambharan 23*0cc7aa89SJeenu Viswambharan .macro define_mmu_enable_func el 24*0cc7aa89SJeenu Viswambharan func enable_mmu_direct_\()el\el 25*0cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 26*0cc7aa89SJeenu Viswambharan _mrs x1, sctlr, \el 27*0cc7aa89SJeenu Viswambharan tst x1, #SCTLR_M_BIT 28*0cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 29*0cc7aa89SJeenu Viswambharan#endif 30*0cc7aa89SJeenu Viswambharan 31*0cc7aa89SJeenu Viswambharan /* Invalidate TLB entries */ 32*0cc7aa89SJeenu Viswambharan .if \el == 1 33*0cc7aa89SJeenu Viswambharan TLB_INVALIDATE(vmalle1) 34*0cc7aa89SJeenu Viswambharan .else 35*0cc7aa89SJeenu Viswambharan .if \el == 3 36*0cc7aa89SJeenu Viswambharan TLB_INVALIDATE(alle3) 37*0cc7aa89SJeenu Viswambharan .else 38*0cc7aa89SJeenu Viswambharan .error "EL must be 1 or 3" 39*0cc7aa89SJeenu Viswambharan .endif 40*0cc7aa89SJeenu Viswambharan .endif 41*0cc7aa89SJeenu Viswambharan 42*0cc7aa89SJeenu Viswambharan mov x7, x0 43*0cc7aa89SJeenu Viswambharan ldr x0, =mmu_cfg_params 44*0cc7aa89SJeenu Viswambharan 45*0cc7aa89SJeenu Viswambharan /* MAIR */ 46*0cc7aa89SJeenu Viswambharan ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)] 47*0cc7aa89SJeenu Viswambharan _msr mair, \el, x1 48*0cc7aa89SJeenu Viswambharan 49*0cc7aa89SJeenu Viswambharan /* TCR */ 50*0cc7aa89SJeenu Viswambharan ldr w2, [x0, #(MMU_CFG_TCR << 2)] 51*0cc7aa89SJeenu Viswambharan _msr tcr, \el, x2 52*0cc7aa89SJeenu Viswambharan 53*0cc7aa89SJeenu Viswambharan /* TTBR */ 54*0cc7aa89SJeenu Viswambharan ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)] 55*0cc7aa89SJeenu Viswambharan ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)] 56*0cc7aa89SJeenu Viswambharan orr x3, x3, x4, lsl #32 57*0cc7aa89SJeenu Viswambharan _msr ttbr0, \el, x3 58*0cc7aa89SJeenu Viswambharan 59*0cc7aa89SJeenu Viswambharan /* 60*0cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 61*0cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 62*0cc7aa89SJeenu Viswambharan * committed before enabling the MMU 63*0cc7aa89SJeenu Viswambharan */ 64*0cc7aa89SJeenu Viswambharan dsb ish 65*0cc7aa89SJeenu Viswambharan isb 66*0cc7aa89SJeenu Viswambharan 67*0cc7aa89SJeenu Viswambharan /* Set and clear required fields of SCTLR */ 68*0cc7aa89SJeenu Viswambharan _mrs x4, sctlr, \el 69*0cc7aa89SJeenu Viswambharan mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 70*0cc7aa89SJeenu Viswambharan orr x4, x4, x5 71*0cc7aa89SJeenu Viswambharan 72*0cc7aa89SJeenu Viswambharan /* Additionally, amend SCTLR fields based on flags */ 73*0cc7aa89SJeenu Viswambharan bic x5, x4, #SCTLR_C_BIT 74*0cc7aa89SJeenu Viswambharan tst x7, #DISABLE_DCACHE 75*0cc7aa89SJeenu Viswambharan csel x4, x5, x4, ne 76*0cc7aa89SJeenu Viswambharan 77*0cc7aa89SJeenu Viswambharan _msr sctlr, \el, x4 78*0cc7aa89SJeenu Viswambharan isb 79*0cc7aa89SJeenu Viswambharan 80*0cc7aa89SJeenu Viswambharan ret 81*0cc7aa89SJeenu Viswambharan endfunc enable_mmu_direct_\()el\el 82*0cc7aa89SJeenu Viswambharan .endm 83*0cc7aa89SJeenu Viswambharan 84*0cc7aa89SJeenu Viswambharan /* 85*0cc7aa89SJeenu Viswambharan * Define MMU-enabling functions for EL1 and EL3: 86*0cc7aa89SJeenu Viswambharan * 87*0cc7aa89SJeenu Viswambharan * enable_mmu_direct_el1 88*0cc7aa89SJeenu Viswambharan * enable_mmu_direct_el3 89*0cc7aa89SJeenu Viswambharan */ 90*0cc7aa89SJeenu Viswambharan define_mmu_enable_func 1 91*0cc7aa89SJeenu Viswambharan define_mmu_enable_func 3 92