1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_features.h> 14 #include <arch_helpers.h> 15 #include <lib/cassert.h> 16 #include <lib/utils_def.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 19 #include "../xlat_tables_private.h" 20 21 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 22 #error ARMv7 target does not support LPAE MMU descriptors 23 #endif 24 25 /* 26 * Returns true if the provided granule size is supported, false otherwise. 27 */ 28 bool xlat_arch_is_granule_size_supported(size_t size) 29 { 30 /* 31 * The library uses the long descriptor translation table format, which 32 * supports 4 KiB pages only. 33 */ 34 return size == PAGE_SIZE_4KB; 35 } 36 37 size_t xlat_arch_get_max_supported_granule_size(void) 38 { 39 return PAGE_SIZE_4KB; 40 } 41 42 #if ENABLE_ASSERTIONS 43 unsigned long long xlat_arch_get_max_supported_pa(void) 44 { 45 /* Physical address space size for long descriptor format. */ 46 return (1ULL << 40) - 1ULL; 47 } 48 #endif /* ENABLE_ASSERTIONS*/ 49 50 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 51 { 52 if (ctx->xlat_regime == EL1_EL0_REGIME) { 53 assert(xlat_arch_current_el() == 1U); 54 return (read_sctlr() & SCTLR_M_BIT) != 0U; 55 } else { 56 assert(ctx->xlat_regime == EL2_REGIME); 57 assert(xlat_arch_current_el() == 2U); 58 return (read_hsctlr() & HSCTLR_M_BIT) != 0U; 59 } 60 } 61 62 bool is_dcache_enabled(void) 63 { 64 if (IS_IN_EL2()) { 65 return (read_hsctlr() & HSCTLR_C_BIT) != 0U; 66 } else { 67 return (read_sctlr() & SCTLR_C_BIT) != 0U; 68 } 69 } 70 71 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime) 72 { 73 if (xlat_regime == EL1_EL0_REGIME) { 74 return UPPER_ATTRS(XN) | UPPER_ATTRS(PXN); 75 } else { 76 assert(xlat_regime == EL2_REGIME); 77 return UPPER_ATTRS(XN); 78 } 79 } 80 81 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime) 82 { 83 /* 84 * Ensure the translation table write has drained into memory before 85 * invalidating the TLB entry. 86 */ 87 dsbishst(); 88 89 if (xlat_regime == EL1_EL0_REGIME) { 90 tlbimvaais(TLBI_ADDR(va)); 91 } else { 92 assert(xlat_regime == EL2_REGIME); 93 tlbimvahis(TLBI_ADDR(va)); 94 } 95 } 96 97 void xlat_arch_tlbi_va_sync(void) 98 { 99 /* Invalidate all entries from branch predictors. */ 100 bpiallis(); 101 102 /* 103 * A TLB maintenance instruction can complete at any time after 104 * it is issued, but is only guaranteed to be complete after the 105 * execution of DSB by the PE that executed the TLB maintenance 106 * instruction. After the TLB invalidate instruction is 107 * complete, no new memory accesses using the invalidated TLB 108 * entries will be observed by any observer of the system 109 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 110 * "Ordering and completion of TLB maintenance instructions". 111 */ 112 dsbish(); 113 114 /* 115 * The effects of a completed TLB maintenance instruction are 116 * only guaranteed to be visible on the PE that executed the 117 * instruction after the execution of an ISB instruction by the 118 * PE that executed the TLB maintenance instruction. 119 */ 120 isb(); 121 } 122 123 unsigned int xlat_arch_current_el(void) 124 { 125 if (IS_IN_HYP()) { 126 return 2U; 127 } else { 128 assert(IS_IN_SVC() || IS_IN_MON()); 129 /* 130 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, 131 * System, SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 132 * 133 * The PL1&0 translation regime in AArch32 behaves like the 134 * EL1&0 regime in AArch64 except for the XN bits, but we set 135 * and unset them at the same time, so there's no difference in 136 * practice. 137 */ 138 return 1U; 139 } 140 } 141 142 /******************************************************************************* 143 * Function for enabling the MMU in PL1 or PL2, assuming that the page tables 144 * have already been created. 145 ******************************************************************************/ 146 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 147 const uint64_t *base_table, unsigned long long max_pa, 148 uintptr_t max_va, __unused int xlat_regime) 149 { 150 uint64_t mair, ttbr0; 151 uint32_t ttbcr; 152 153 /* Set attributes in the right indices of the MAIR */ 154 mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 155 mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 156 ATTR_IWBWA_OWBWA_NTR_INDEX); 157 mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 158 ATTR_NON_CACHEABLE_INDEX); 159 160 /* 161 * Configure the control register for stage 1 of the PL1&0 or EL2 162 * translation regimes. 163 */ 164 165 /* Use the Long-descriptor translation table format. */ 166 ttbcr = TTBCR_EAE_BIT; 167 168 if (xlat_regime == EL1_EL0_REGIME) { 169 assert(IS_IN_SVC() || IS_IN_MON()); 170 /* 171 * Disable translation table walk for addresses that are 172 * translated using TTBR1. Therefore, only TTBR0 is used. 173 */ 174 ttbcr |= TTBCR_EPD1_BIT; 175 } else { 176 assert(xlat_regime == EL2_REGIME); 177 assert(IS_IN_HYP()); 178 179 /* 180 * Set HTCR bits as well. Set HTTBR table properties 181 * as Inner & outer WBWA & shareable. 182 */ 183 ttbcr |= HTCR_RES1 | 184 HTCR_SH0_INNER_SHAREABLE | HTCR_RGN0_OUTER_WBA | 185 HTCR_RGN0_INNER_WBA; 186 } 187 188 /* 189 * Limit the input address ranges and memory region sizes translated 190 * using TTBR0 to the given virtual address space size, if smaller than 191 * 32 bits. 192 */ 193 if (max_va != UINT32_MAX) { 194 uintptr_t virtual_addr_space_size = max_va + 1U; 195 196 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 197 /* 198 * __builtin_ctzll(0) is undefined but here we are guaranteed 199 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 200 */ 201 int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size); 202 203 ttbcr |= (uint32_t) t0sz; 204 } 205 206 /* 207 * Set the cacheability and shareability attributes for memory 208 * associated with translation table walks using TTBR0. 209 */ 210 if ((flags & XLAT_TABLE_NC) != 0U) { 211 /* Inner & outer non-cacheable non-shareable. */ 212 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 213 TTBCR_RGN0_INNER_NC; 214 } else { 215 /* Inner & outer WBWA & shareable. */ 216 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 217 TTBCR_RGN0_INNER_WBA; 218 } 219 220 /* Set TTBR0 bits as well */ 221 ttbr0 = (uint64_t)(uintptr_t) base_table; 222 223 if (is_armv8_2_ttcnp_present()) { 224 /* Enable CnP bit so as to share page tables with all PEs. */ 225 ttbr0 |= TTBR_CNP_BIT; 226 } 227 228 /* Now populate MMU configuration */ 229 params[MMU_CFG_MAIR] = mair; 230 params[MMU_CFG_TCR] = (uint64_t) ttbcr; 231 params[MMU_CFG_TTBR0] = ttbr0; 232 } 233