1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 18 #error ARMv7 target does not support LPAE MMU descriptors 19 #endif 20 21 uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; 22 23 /* 24 * Returns 1 if the provided granule size is supported, 0 otherwise. 25 */ 26 int xlat_arch_is_granule_size_supported(size_t size) 27 { 28 /* 29 * The Trusted Firmware uses long descriptor translation table format, 30 * which supports 4 KiB pages only. 31 */ 32 return (size == (4U * 1024U)); 33 } 34 35 size_t xlat_arch_get_max_supported_granule_size(void) 36 { 37 return 4U * 1024U; 38 } 39 40 #if ENABLE_ASSERTIONS 41 unsigned long long xlat_arch_get_max_supported_pa(void) 42 { 43 /* Physical address space size for long descriptor format. */ 44 return (1ULL << 40) - 1ULL; 45 } 46 #endif /* ENABLE_ASSERTIONS*/ 47 48 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused) 49 { 50 return (read_sctlr() & SCTLR_M_BIT) != 0; 51 } 52 53 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime __unused) 54 { 55 return UPPER_ATTRS(XN); 56 } 57 58 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime __unused) 59 { 60 /* 61 * Ensure the translation table write has drained into memory before 62 * invalidating the TLB entry. 63 */ 64 dsbishst(); 65 66 tlbimvaais(TLBI_ADDR(va)); 67 } 68 69 void xlat_arch_tlbi_va_sync(void) 70 { 71 /* Invalidate all entries from branch predictors. */ 72 bpiallis(); 73 74 /* 75 * A TLB maintenance instruction can complete at any time after 76 * it is issued, but is only guaranteed to be complete after the 77 * execution of DSB by the PE that executed the TLB maintenance 78 * instruction. After the TLB invalidate instruction is 79 * complete, no new memory accesses using the invalidated TLB 80 * entries will be observed by any observer of the system 81 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 82 * "Ordering and completion of TLB maintenance instructions". 83 */ 84 dsbish(); 85 86 /* 87 * The effects of a completed TLB maintenance instruction are 88 * only guaranteed to be visible on the PE that executed the 89 * instruction after the execution of an ISB instruction by the 90 * PE that executed the TLB maintenance instruction. 91 */ 92 isb(); 93 } 94 95 int xlat_arch_current_el(void) 96 { 97 /* 98 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 99 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 100 */ 101 return 3; 102 } 103 104 /******************************************************************************* 105 * Function for enabling the MMU in Secure PL1, assuming that the page tables 106 * have already been created. 107 ******************************************************************************/ 108 void setup_mmu_cfg(unsigned int flags, 109 const uint64_t *base_table, 110 unsigned long long max_pa, 111 uintptr_t max_va) 112 { 113 u_register_t mair0, ttbcr; 114 uint64_t ttbr0; 115 116 assert(IS_IN_SECURE()); 117 118 /* Set attributes in the right indices of the MAIR */ 119 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 120 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 121 ATTR_IWBWA_OWBWA_NTR_INDEX); 122 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 123 ATTR_NON_CACHEABLE_INDEX); 124 125 /* 126 * Configure the control register for stage 1 of the PL1&0 translation 127 * regime. 128 */ 129 130 /* Use the Long-descriptor translation table format. */ 131 ttbcr = TTBCR_EAE_BIT; 132 133 /* 134 * Disable translation table walk for addresses that are translated 135 * using TTBR1. Therefore, only TTBR0 is used. 136 */ 137 ttbcr |= TTBCR_EPD1_BIT; 138 139 /* 140 * Limit the input address ranges and memory region sizes translated 141 * using TTBR0 to the given virtual address space size, if smaller than 142 * 32 bits. 143 */ 144 if (max_va != UINT32_MAX) { 145 uintptr_t virtual_addr_space_size = max_va + 1; 146 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 147 /* 148 * __builtin_ctzll(0) is undefined but here we are guaranteed 149 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 150 */ 151 ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size); 152 } 153 154 /* 155 * Set the cacheability and shareability attributes for memory 156 * associated with translation table walks using TTBR0. 157 */ 158 if (flags & XLAT_TABLE_NC) { 159 /* Inner & outer non-cacheable non-shareable. */ 160 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 161 TTBCR_RGN0_INNER_NC; 162 } else { 163 /* Inner & outer WBWA & shareable. */ 164 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 165 TTBCR_RGN0_INNER_WBA; 166 } 167 168 /* Set TTBR0 bits as well */ 169 ttbr0 = (uint64_t)(uintptr_t) base_table; 170 #if ARM_ARCH_AT_LEAST(8, 2) 171 /* 172 * Enable CnP bit so as to share page tables with all PEs. 173 * Mandatory for ARMv8.2 implementations. 174 */ 175 ttbr0 |= TTBR_CNP_BIT; 176 #endif 177 178 /* Now populate MMU configuration */ 179 mmu_cfg_params[MMU_CFG_MAIR0] = mair0; 180 mmu_cfg_params[MMU_CFG_TCR] = ttbcr; 181 mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr0; 182 mmu_cfg_params[MMU_CFG_TTBR0_HI] = ttbr0 >> 32; 183 } 184