1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <xlat_tables_v2.h> 14 #include "../xlat_tables_private.h" 15 16 #if ENABLE_ASSERTIONS 17 unsigned long long xlat_arch_get_max_supported_pa(void) 18 { 19 /* Physical address space size for long descriptor format. */ 20 return (1ull << 40) - 1ull; 21 } 22 #endif /* ENABLE_ASSERTIONS*/ 23 24 int is_mmu_enabled(void) 25 { 26 return (read_sctlr() & SCTLR_M_BIT) != 0; 27 } 28 29 #if PLAT_XLAT_TABLES_DYNAMIC 30 31 void xlat_arch_tlbi_va(uintptr_t va) 32 { 33 /* 34 * Ensure the translation table write has drained into memory before 35 * invalidating the TLB entry. 36 */ 37 dsbishst(); 38 39 tlbimvaais(TLBI_ADDR(va)); 40 } 41 42 void xlat_arch_tlbi_va_sync(void) 43 { 44 /* Invalidate all entries from branch predictors. */ 45 bpiallis(); 46 47 /* 48 * A TLB maintenance instruction can complete at any time after 49 * it is issued, but is only guaranteed to be complete after the 50 * execution of DSB by the PE that executed the TLB maintenance 51 * instruction. After the TLB invalidate instruction is 52 * complete, no new memory accesses using the invalidated TLB 53 * entries will be observed by any observer of the system 54 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 55 * "Ordering and completion of TLB maintenance instructions". 56 */ 57 dsbish(); 58 59 /* 60 * The effects of a completed TLB maintenance instruction are 61 * only guaranteed to be visible on the PE that executed the 62 * instruction after the execution of an ISB instruction by the 63 * PE that executed the TLB maintenance instruction. 64 */ 65 isb(); 66 } 67 68 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 69 70 int xlat_arch_current_el(void) 71 { 72 /* 73 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 74 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 75 */ 76 return 3; 77 } 78 79 uint64_t xlat_arch_get_xn_desc(int el __unused) 80 { 81 return UPPER_ATTRS(XN); 82 } 83 84 /******************************************************************************* 85 * Function for enabling the MMU in Secure PL1, assuming that the page tables 86 * have already been created. 87 ******************************************************************************/ 88 void enable_mmu_arch(unsigned int flags, 89 uint64_t *base_table, 90 unsigned long long max_pa, 91 uintptr_t max_va) 92 { 93 u_register_t mair0, ttbcr, sctlr; 94 uint64_t ttbr0; 95 96 assert(IS_IN_SECURE()); 97 98 sctlr = read_sctlr(); 99 assert((sctlr & SCTLR_M_BIT) == 0); 100 101 /* Invalidate TLBs at the current exception level */ 102 tlbiall(); 103 104 /* Set attributes in the right indices of the MAIR */ 105 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 106 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 107 ATTR_IWBWA_OWBWA_NTR_INDEX); 108 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 109 ATTR_NON_CACHEABLE_INDEX); 110 111 /* 112 * Configure the control register for stage 1 of the PL1&0 translation 113 * regime. 114 */ 115 116 /* Use the Long-descriptor translation table format. */ 117 ttbcr = TTBCR_EAE_BIT; 118 119 /* 120 * Disable translation table walk for addresses that are translated 121 * using TTBR1. Therefore, only TTBR0 is used. 122 */ 123 ttbcr |= TTBCR_EPD1_BIT; 124 125 /* 126 * Limit the input address ranges and memory region sizes translated 127 * using TTBR0 to the given virtual address space size, if smaller than 128 * 32 bits. 129 */ 130 if (max_va != UINT32_MAX) { 131 uintptr_t virtual_addr_space_size = max_va + 1; 132 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 133 /* 134 * __builtin_ctzl(0) is undefined but here we are guaranteed 135 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 136 */ 137 ttbcr |= 32 - __builtin_ctzl(virtual_addr_space_size); 138 } 139 140 /* 141 * Set the cacheability and shareability attributes for memory 142 * associated with translation table walks using TTBR0. 143 */ 144 if (flags & XLAT_TABLE_NC) { 145 /* Inner & outer non-cacheable non-shareable. */ 146 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 147 TTBCR_RGN0_INNER_NC; 148 } else { 149 /* Inner & outer WBWA & shareable. */ 150 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 151 TTBCR_RGN0_INNER_WBA; 152 } 153 154 /* Set TTBR0 bits as well */ 155 ttbr0 = (uint64_t)(uintptr_t) base_table; 156 157 /* Now program the relevant system registers */ 158 write_mair0(mair0); 159 write_ttbcr(ttbcr); 160 write64_ttbr0(ttbr0); 161 write64_ttbr1(0); 162 163 /* 164 * Ensure all translation table writes have drained 165 * into memory, the TLB invalidation is complete, 166 * and translation register writes are committed 167 * before enabling the MMU 168 */ 169 dsbish(); 170 isb(); 171 172 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 173 174 if (flags & DISABLE_DCACHE) 175 sctlr &= ~SCTLR_C_BIT; 176 else 177 sctlr |= SCTLR_C_BIT; 178 179 write_sctlr(sctlr); 180 181 /* Ensure the MMU enable takes effect immediately */ 182 isb(); 183 } 184