1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <stdbool.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 18 #error ARMv7 target does not support LPAE MMU descriptors 19 #endif 20 21 /* 22 * Returns true if the provided granule size is supported, false otherwise. 23 */ 24 bool xlat_arch_is_granule_size_supported(size_t size) 25 { 26 /* 27 * The library uses the long descriptor translation table format, which 28 * supports 4 KiB pages only. 29 */ 30 return size == PAGE_SIZE_4KB; 31 } 32 33 size_t xlat_arch_get_max_supported_granule_size(void) 34 { 35 return PAGE_SIZE_4KB; 36 } 37 38 #if ENABLE_ASSERTIONS 39 unsigned long long xlat_arch_get_max_supported_pa(void) 40 { 41 /* Physical address space size for long descriptor format. */ 42 return (1ULL << 40) - 1ULL; 43 } 44 #endif /* ENABLE_ASSERTIONS*/ 45 46 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused) 47 { 48 return (read_sctlr() & SCTLR_M_BIT) != 0; 49 } 50 51 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime __unused) 52 { 53 return UPPER_ATTRS(XN); 54 } 55 56 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime __unused) 57 { 58 /* 59 * Ensure the translation table write has drained into memory before 60 * invalidating the TLB entry. 61 */ 62 dsbishst(); 63 64 tlbimvaais(TLBI_ADDR(va)); 65 } 66 67 void xlat_arch_tlbi_va_sync(void) 68 { 69 /* Invalidate all entries from branch predictors. */ 70 bpiallis(); 71 72 /* 73 * A TLB maintenance instruction can complete at any time after 74 * it is issued, but is only guaranteed to be complete after the 75 * execution of DSB by the PE that executed the TLB maintenance 76 * instruction. After the TLB invalidate instruction is 77 * complete, no new memory accesses using the invalidated TLB 78 * entries will be observed by any observer of the system 79 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 80 * "Ordering and completion of TLB maintenance instructions". 81 */ 82 dsbish(); 83 84 /* 85 * The effects of a completed TLB maintenance instruction are 86 * only guaranteed to be visible on the PE that executed the 87 * instruction after the execution of an ISB instruction by the 88 * PE that executed the TLB maintenance instruction. 89 */ 90 isb(); 91 } 92 93 unsigned int xlat_arch_current_el(void) 94 { 95 /* 96 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 97 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 98 * 99 * The PL1&0 translation regime in AArch32 behaves like the EL1&0 regime 100 * in AArch64 except for the XN bits, but we set and unset them at the 101 * same time, so there's no difference in practice. 102 */ 103 return 1U; 104 } 105 106 /******************************************************************************* 107 * Function for enabling the MMU in Secure PL1, assuming that the page tables 108 * have already been created. 109 ******************************************************************************/ 110 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 111 const uint64_t *base_table, unsigned long long max_pa, 112 uintptr_t max_va, __unused int xlat_regime) 113 { 114 uint64_t mair, ttbr0; 115 uint32_t ttbcr; 116 117 assert(IS_IN_SECURE()); 118 119 /* Set attributes in the right indices of the MAIR */ 120 mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 121 mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 122 ATTR_IWBWA_OWBWA_NTR_INDEX); 123 mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 124 ATTR_NON_CACHEABLE_INDEX); 125 126 /* 127 * Configure the control register for stage 1 of the PL1&0 translation 128 * regime. 129 */ 130 131 /* Use the Long-descriptor translation table format. */ 132 ttbcr = TTBCR_EAE_BIT; 133 134 /* 135 * Disable translation table walk for addresses that are translated 136 * using TTBR1. Therefore, only TTBR0 is used. 137 */ 138 ttbcr |= TTBCR_EPD1_BIT; 139 140 /* 141 * Limit the input address ranges and memory region sizes translated 142 * using TTBR0 to the given virtual address space size, if smaller than 143 * 32 bits. 144 */ 145 if (max_va != UINT32_MAX) { 146 uintptr_t virtual_addr_space_size = max_va + 1U; 147 148 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 149 /* 150 * __builtin_ctzll(0) is undefined but here we are guaranteed 151 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 152 */ 153 int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size); 154 155 ttbcr |= (uint32_t) t0sz; 156 } 157 158 /* 159 * Set the cacheability and shareability attributes for memory 160 * associated with translation table walks using TTBR0. 161 */ 162 if ((flags & XLAT_TABLE_NC) != 0U) { 163 /* Inner & outer non-cacheable non-shareable. */ 164 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 165 TTBCR_RGN0_INNER_NC; 166 } else { 167 /* Inner & outer WBWA & shareable. */ 168 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 169 TTBCR_RGN0_INNER_WBA; 170 } 171 172 /* Set TTBR0 bits as well */ 173 ttbr0 = (uint64_t)(uintptr_t) base_table; 174 175 #if ARM_ARCH_AT_LEAST(8, 2) 176 /* 177 * Enable CnP bit so as to share page tables with all PEs. This 178 * is mandatory for ARMv8.2 implementations. 179 */ 180 ttbr0 |= TTBR_CNP_BIT; 181 #endif 182 183 /* Now populate MMU configuration */ 184 params[MMU_CFG_MAIR] = mair; 185 params[MMU_CFG_TCR] = (uint64_t) ttbcr; 186 params[MMU_CFG_TTBR0] = ttbr0; 187 } 188