1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 18 #error ARMv7 target does not support LPAE MMU descriptors 19 #endif 20 21 #if ENABLE_ASSERTIONS 22 unsigned long long xlat_arch_get_max_supported_pa(void) 23 { 24 /* Physical address space size for long descriptor format. */ 25 return (1ULL << 40) - 1ULL; 26 } 27 #endif /* ENABLE_ASSERTIONS*/ 28 29 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused) 30 { 31 return (read_sctlr() & SCTLR_M_BIT) != 0; 32 } 33 34 void xlat_arch_tlbi_va(uintptr_t va) 35 { 36 /* 37 * Ensure the translation table write has drained into memory before 38 * invalidating the TLB entry. 39 */ 40 dsbishst(); 41 42 tlbimvaais(TLBI_ADDR(va)); 43 } 44 45 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime __unused) 46 { 47 /* 48 * Ensure the translation table write has drained into memory before 49 * invalidating the TLB entry. 50 */ 51 dsbishst(); 52 53 tlbimvaais(TLBI_ADDR(va)); 54 } 55 56 void xlat_arch_tlbi_va_sync(void) 57 { 58 /* Invalidate all entries from branch predictors. */ 59 bpiallis(); 60 61 /* 62 * A TLB maintenance instruction can complete at any time after 63 * it is issued, but is only guaranteed to be complete after the 64 * execution of DSB by the PE that executed the TLB maintenance 65 * instruction. After the TLB invalidate instruction is 66 * complete, no new memory accesses using the invalidated TLB 67 * entries will be observed by any observer of the system 68 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 69 * "Ordering and completion of TLB maintenance instructions". 70 */ 71 dsbish(); 72 73 /* 74 * The effects of a completed TLB maintenance instruction are 75 * only guaranteed to be visible on the PE that executed the 76 * instruction after the execution of an ISB instruction by the 77 * PE that executed the TLB maintenance instruction. 78 */ 79 isb(); 80 } 81 82 int xlat_arch_current_el(void) 83 { 84 /* 85 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 86 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 87 */ 88 return 3; 89 } 90 91 /******************************************************************************* 92 * Function for enabling the MMU in Secure PL1, assuming that the page tables 93 * have already been created. 94 ******************************************************************************/ 95 void enable_mmu_arch(unsigned int flags, 96 uint64_t *base_table, 97 unsigned long long max_pa, 98 uintptr_t max_va) 99 { 100 u_register_t mair0, ttbcr, sctlr; 101 uint64_t ttbr0; 102 103 assert(IS_IN_SECURE()); 104 105 sctlr = read_sctlr(); 106 assert((sctlr & SCTLR_M_BIT) == 0); 107 108 /* Invalidate TLBs at the current exception level */ 109 tlbiall(); 110 111 /* Set attributes in the right indices of the MAIR */ 112 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 113 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 114 ATTR_IWBWA_OWBWA_NTR_INDEX); 115 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 116 ATTR_NON_CACHEABLE_INDEX); 117 118 /* 119 * Configure the control register for stage 1 of the PL1&0 translation 120 * regime. 121 */ 122 123 /* Use the Long-descriptor translation table format. */ 124 ttbcr = TTBCR_EAE_BIT; 125 126 /* 127 * Disable translation table walk for addresses that are translated 128 * using TTBR1. Therefore, only TTBR0 is used. 129 */ 130 ttbcr |= TTBCR_EPD1_BIT; 131 132 /* 133 * Limit the input address ranges and memory region sizes translated 134 * using TTBR0 to the given virtual address space size, if smaller than 135 * 32 bits. 136 */ 137 if (max_va != UINT32_MAX) { 138 uintptr_t virtual_addr_space_size = max_va + 1; 139 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 140 /* 141 * __builtin_ctzll(0) is undefined but here we are guaranteed 142 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 143 */ 144 ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size); 145 } 146 147 /* 148 * Set the cacheability and shareability attributes for memory 149 * associated with translation table walks using TTBR0. 150 */ 151 if (flags & XLAT_TABLE_NC) { 152 /* Inner & outer non-cacheable non-shareable. */ 153 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 154 TTBCR_RGN0_INNER_NC; 155 } else { 156 /* Inner & outer WBWA & shareable. */ 157 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 158 TTBCR_RGN0_INNER_WBA; 159 } 160 161 /* Set TTBR0 bits as well */ 162 ttbr0 = (uint64_t)(uintptr_t) base_table; 163 #if ARM_ARCH_AT_LEAST(8, 2) 164 /* 165 * Enable CnP bit so as to share page tables with all PEs. 166 * Mandatory for ARMv8.2 implementations. 167 */ 168 ttbr0 |= TTBR_CNP_BIT; 169 #endif 170 171 /* Now program the relevant system registers */ 172 write_mair0(mair0); 173 write_ttbcr(ttbcr); 174 write64_ttbr0(ttbr0); 175 write64_ttbr1(0); 176 177 /* 178 * Ensure all translation table writes have drained 179 * into memory, the TLB invalidation is complete, 180 * and translation register writes are committed 181 * before enabling the MMU 182 */ 183 dsbish(); 184 isb(); 185 186 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 187 188 if (flags & DISABLE_DCACHE) 189 sctlr &= ~SCTLR_C_BIT; 190 else 191 sctlr |= SCTLR_C_BIT; 192 193 write_sctlr(sctlr); 194 195 /* Ensure the MMU enable takes effect immediately */ 196 isb(); 197 } 198