1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if ENABLE_ASSERTIONS 18 unsigned long long xlat_arch_get_max_supported_pa(void) 19 { 20 /* Physical address space size for long descriptor format. */ 21 return (1ull << 40) - 1ull; 22 } 23 #endif /* ENABLE_ASSERTIONS*/ 24 25 int is_mmu_enabled(void) 26 { 27 return (read_sctlr() & SCTLR_M_BIT) != 0; 28 } 29 30 #if PLAT_XLAT_TABLES_DYNAMIC 31 32 void xlat_arch_tlbi_va(uintptr_t va) 33 { 34 /* 35 * Ensure the translation table write has drained into memory before 36 * invalidating the TLB entry. 37 */ 38 dsbishst(); 39 40 tlbimvaais(TLBI_ADDR(va)); 41 } 42 43 void xlat_arch_tlbi_va_sync(void) 44 { 45 /* Invalidate all entries from branch predictors. */ 46 bpiallis(); 47 48 /* 49 * A TLB maintenance instruction can complete at any time after 50 * it is issued, but is only guaranteed to be complete after the 51 * execution of DSB by the PE that executed the TLB maintenance 52 * instruction. After the TLB invalidate instruction is 53 * complete, no new memory accesses using the invalidated TLB 54 * entries will be observed by any observer of the system 55 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 56 * "Ordering and completion of TLB maintenance instructions". 57 */ 58 dsbish(); 59 60 /* 61 * The effects of a completed TLB maintenance instruction are 62 * only guaranteed to be visible on the PE that executed the 63 * instruction after the execution of an ISB instruction by the 64 * PE that executed the TLB maintenance instruction. 65 */ 66 isb(); 67 } 68 69 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 70 71 int xlat_arch_current_el(void) 72 { 73 /* 74 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 75 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 76 */ 77 return 3; 78 } 79 80 uint64_t xlat_arch_get_xn_desc(int el __unused) 81 { 82 return UPPER_ATTRS(XN); 83 } 84 85 /******************************************************************************* 86 * Function for enabling the MMU in Secure PL1, assuming that the page tables 87 * have already been created. 88 ******************************************************************************/ 89 void enable_mmu_arch(unsigned int flags, 90 uint64_t *base_table, 91 unsigned long long max_pa, 92 uintptr_t max_va) 93 { 94 u_register_t mair0, ttbcr, sctlr; 95 uint64_t ttbr0; 96 97 assert(IS_IN_SECURE()); 98 99 sctlr = read_sctlr(); 100 assert((sctlr & SCTLR_M_BIT) == 0); 101 102 /* Invalidate TLBs at the current exception level */ 103 tlbiall(); 104 105 /* Set attributes in the right indices of the MAIR */ 106 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 107 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 108 ATTR_IWBWA_OWBWA_NTR_INDEX); 109 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 110 ATTR_NON_CACHEABLE_INDEX); 111 112 /* 113 * Configure the control register for stage 1 of the PL1&0 translation 114 * regime. 115 */ 116 117 /* Use the Long-descriptor translation table format. */ 118 ttbcr = TTBCR_EAE_BIT; 119 120 /* 121 * Disable translation table walk for addresses that are translated 122 * using TTBR1. Therefore, only TTBR0 is used. 123 */ 124 ttbcr |= TTBCR_EPD1_BIT; 125 126 /* 127 * Limit the input address ranges and memory region sizes translated 128 * using TTBR0 to the given virtual address space size, if smaller than 129 * 32 bits. 130 */ 131 if (max_va != UINT32_MAX) { 132 uintptr_t virtual_addr_space_size = max_va + 1; 133 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 134 /* 135 * __builtin_ctzll(0) is undefined but here we are guaranteed 136 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 137 */ 138 ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size); 139 } 140 141 /* 142 * Set the cacheability and shareability attributes for memory 143 * associated with translation table walks using TTBR0. 144 */ 145 if (flags & XLAT_TABLE_NC) { 146 /* Inner & outer non-cacheable non-shareable. */ 147 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 148 TTBCR_RGN0_INNER_NC; 149 } else { 150 /* Inner & outer WBWA & shareable. */ 151 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 152 TTBCR_RGN0_INNER_WBA; 153 } 154 155 /* Set TTBR0 bits as well */ 156 ttbr0 = (uint64_t)(uintptr_t) base_table; 157 #if ARM_ARCH_AT_LEAST(8, 2) 158 /* 159 * Enable CnP bit so as to share page tables with all PEs. 160 * Mandatory for ARMv8.2 implementations. 161 */ 162 ttbr0 |= TTBR_CNP_BIT; 163 #endif 164 165 /* Now program the relevant system registers */ 166 write_mair0(mair0); 167 write_ttbcr(ttbcr); 168 write64_ttbr0(ttbr0); 169 write64_ttbr1(0); 170 171 /* 172 * Ensure all translation table writes have drained 173 * into memory, the TLB invalidation is complete, 174 * and translation register writes are committed 175 * before enabling the MMU 176 */ 177 dsbish(); 178 isb(); 179 180 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 181 182 if (flags & DISABLE_DCACHE) 183 sctlr &= ~SCTLR_C_BIT; 184 else 185 sctlr |= SCTLR_C_BIT; 186 187 write_sctlr(sctlr); 188 189 /* Ensure the MMU enable takes effect immediately */ 190 isb(); 191 } 192