1/* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <xlat_tables_v2.h> 10 11 .global enable_mmu_direct 12 13func enable_mmu_direct 14 /* Assert that MMU is turned off */ 15#if ENABLE_ASSERTIONS 16 ldcopr r1, SCTLR 17 tst r1, #SCTLR_M_BIT 18 ASM_ASSERT(eq) 19#endif 20 21 /* Invalidate TLB entries */ 22 TLB_INVALIDATE(r0, TLBIALL) 23 24 mov r3, r0 25 ldr r0, =mmu_cfg_params 26 27 /* MAIR0. Only the lower 32 bits are used. */ 28 ldr r1, [r0, #(MMU_CFG_MAIR << 3)] 29 stcopr r1, MAIR0 30 31 /* TTBCR. Only the lower 32 bits are used. */ 32 ldr r2, [r0, #(MMU_CFG_TCR << 3)] 33 stcopr r2, TTBCR 34 35 /* TTBR0 */ 36 ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)] 37 ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)] 38 stcopr16 r1, r2, TTBR0_64 39 40 /* TTBR1 is unused right now; set it to 0. */ 41 mov r1, #0 42 mov r2, #0 43 stcopr16 r1, r2, TTBR1_64 44 45 /* 46 * Ensure all translation table writes have drained into memory, the TLB 47 * invalidation is complete, and translation register writes are 48 * committed before enabling the MMU 49 */ 50 dsb ish 51 isb 52 53 /* Enable enable MMU by honoring flags */ 54 ldcopr r1, SCTLR 55 ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) 56 orr r1, r1, r2 57 58 /* Clear C bit if requested */ 59 tst r3, #DISABLE_DCACHE 60 bicne r1, r1, #SCTLR_C_BIT 61 62 stcopr r1, SCTLR 63 isb 64 65 bx lr 66endfunc enable_mmu_direct 67