10cc7aa89SJeenu Viswambharan/* 20cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 30cc7aa89SJeenu Viswambharan * 40cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 50cc7aa89SJeenu Viswambharan */ 60cc7aa89SJeenu Viswambharan 70cc7aa89SJeenu Viswambharan#include <asm_macros.S> 80cc7aa89SJeenu Viswambharan#include <assert_macros.S> 90cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 100cc7aa89SJeenu Viswambharan 110cc7aa89SJeenu Viswambharan .global enable_mmu_direct 120cc7aa89SJeenu Viswambharan 130cc7aa89SJeenu Viswambharanfunc enable_mmu_direct 140cc7aa89SJeenu Viswambharan /* Assert that MMU is turned off */ 150cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 160cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 170cc7aa89SJeenu Viswambharan tst r1, #SCTLR_M_BIT 180cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 190cc7aa89SJeenu Viswambharan#endif 200cc7aa89SJeenu Viswambharan 210cc7aa89SJeenu Viswambharan /* Invalidate TLB entries */ 220cc7aa89SJeenu Viswambharan TLB_INVALIDATE(r0, TLBIALL) 230cc7aa89SJeenu Viswambharan 240cc7aa89SJeenu Viswambharan mov r3, r0 250cc7aa89SJeenu Viswambharan ldr r0, =mmu_cfg_params 260cc7aa89SJeenu Viswambharan 27*6563c0beSAntonio Nino Diaz /* MAIR0. Only the lower 32 bits are used. */ 28*6563c0beSAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_MAIR << 3)] 290cc7aa89SJeenu Viswambharan stcopr r1, MAIR0 300cc7aa89SJeenu Viswambharan 31*6563c0beSAntonio Nino Diaz /* TTBCR. Only the lower 32 bits are used. */ 32*6563c0beSAntonio Nino Diaz ldr r2, [r0, #(MMU_CFG_TCR << 3)] 330cc7aa89SJeenu Viswambharan stcopr r2, TTBCR 340cc7aa89SJeenu Viswambharan 350cc7aa89SJeenu Viswambharan /* TTBR0 */ 36*6563c0beSAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)] 37*6563c0beSAntonio Nino Diaz ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)] 380cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR0_64 390cc7aa89SJeenu Viswambharan 400cc7aa89SJeenu Viswambharan /* TTBR1 is unused right now; set it to 0. */ 410cc7aa89SJeenu Viswambharan mov r1, #0 420cc7aa89SJeenu Viswambharan mov r2, #0 430cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR1_64 440cc7aa89SJeenu Viswambharan 450cc7aa89SJeenu Viswambharan /* 460cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 470cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 480cc7aa89SJeenu Viswambharan * committed before enabling the MMU 490cc7aa89SJeenu Viswambharan */ 500cc7aa89SJeenu Viswambharan dsb ish 510cc7aa89SJeenu Viswambharan isb 520cc7aa89SJeenu Viswambharan 530cc7aa89SJeenu Viswambharan /* Enable enable MMU by honoring flags */ 540cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 550cc7aa89SJeenu Viswambharan ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) 560cc7aa89SJeenu Viswambharan orr r1, r1, r2 570cc7aa89SJeenu Viswambharan 580cc7aa89SJeenu Viswambharan /* Clear C bit if requested */ 590cc7aa89SJeenu Viswambharan tst r3, #DISABLE_DCACHE 600cc7aa89SJeenu Viswambharan bicne r1, r1, #SCTLR_C_BIT 610cc7aa89SJeenu Viswambharan 620cc7aa89SJeenu Viswambharan stcopr r1, SCTLR 630cc7aa89SJeenu Viswambharan isb 640cc7aa89SJeenu Viswambharan 650cc7aa89SJeenu Viswambharan bx lr 660cc7aa89SJeenu Viswambharanendfunc enable_mmu_direct 67