10cc7aa89SJeenu Viswambharan/* 20cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 30cc7aa89SJeenu Viswambharan * 40cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 50cc7aa89SJeenu Viswambharan */ 60cc7aa89SJeenu Viswambharan 70cc7aa89SJeenu Viswambharan#include <asm_macros.S> 80cc7aa89SJeenu Viswambharan#include <assert_macros.S> 90cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 100cc7aa89SJeenu Viswambharan 11*1a92a0e0SAntonio Nino Diaz .global enable_mmu_direct_svc_mon 12*1a92a0e0SAntonio Nino Diaz .global enable_mmu_direct_hyp 130cc7aa89SJeenu Viswambharan 14*1a92a0e0SAntonio Nino Diaz /* void enable_mmu_direct_svc_mon(unsigned int flags) */ 15*1a92a0e0SAntonio Nino Diazfunc enable_mmu_direct_svc_mon 160cc7aa89SJeenu Viswambharan /* Assert that MMU is turned off */ 170cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 180cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 190cc7aa89SJeenu Viswambharan tst r1, #SCTLR_M_BIT 200cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 210cc7aa89SJeenu Viswambharan#endif 220cc7aa89SJeenu Viswambharan 230cc7aa89SJeenu Viswambharan /* Invalidate TLB entries */ 240cc7aa89SJeenu Viswambharan TLB_INVALIDATE(r0, TLBIALL) 250cc7aa89SJeenu Viswambharan 260cc7aa89SJeenu Viswambharan mov r3, r0 270cc7aa89SJeenu Viswambharan ldr r0, =mmu_cfg_params 280cc7aa89SJeenu Viswambharan 296563c0beSAntonio Nino Diaz /* MAIR0. Only the lower 32 bits are used. */ 306563c0beSAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_MAIR << 3)] 310cc7aa89SJeenu Viswambharan stcopr r1, MAIR0 320cc7aa89SJeenu Viswambharan 336563c0beSAntonio Nino Diaz /* TTBCR. Only the lower 32 bits are used. */ 346563c0beSAntonio Nino Diaz ldr r2, [r0, #(MMU_CFG_TCR << 3)] 350cc7aa89SJeenu Viswambharan stcopr r2, TTBCR 360cc7aa89SJeenu Viswambharan 370cc7aa89SJeenu Viswambharan /* TTBR0 */ 386563c0beSAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)] 396563c0beSAntonio Nino Diaz ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)] 400cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR0_64 410cc7aa89SJeenu Viswambharan 420cc7aa89SJeenu Viswambharan /* TTBR1 is unused right now; set it to 0. */ 430cc7aa89SJeenu Viswambharan mov r1, #0 440cc7aa89SJeenu Viswambharan mov r2, #0 450cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR1_64 460cc7aa89SJeenu Viswambharan 470cc7aa89SJeenu Viswambharan /* 480cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 490cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 500cc7aa89SJeenu Viswambharan * committed before enabling the MMU 510cc7aa89SJeenu Viswambharan */ 520cc7aa89SJeenu Viswambharan dsb ish 530cc7aa89SJeenu Viswambharan isb 540cc7aa89SJeenu Viswambharan 550cc7aa89SJeenu Viswambharan /* Enable enable MMU by honoring flags */ 560cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 570cc7aa89SJeenu Viswambharan ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) 580cc7aa89SJeenu Viswambharan orr r1, r1, r2 590cc7aa89SJeenu Viswambharan 600cc7aa89SJeenu Viswambharan /* Clear C bit if requested */ 610cc7aa89SJeenu Viswambharan tst r3, #DISABLE_DCACHE 620cc7aa89SJeenu Viswambharan bicne r1, r1, #SCTLR_C_BIT 630cc7aa89SJeenu Viswambharan 640cc7aa89SJeenu Viswambharan stcopr r1, SCTLR 650cc7aa89SJeenu Viswambharan isb 660cc7aa89SJeenu Viswambharan 670cc7aa89SJeenu Viswambharan bx lr 68*1a92a0e0SAntonio Nino Diazendfunc enable_mmu_direct_svc_mon 69*1a92a0e0SAntonio Nino Diaz 70*1a92a0e0SAntonio Nino Diaz 71*1a92a0e0SAntonio Nino Diaz /* void enable_mmu_direct_hyp(unsigned int flags) */ 72*1a92a0e0SAntonio Nino Diazfunc enable_mmu_direct_hyp 73*1a92a0e0SAntonio Nino Diaz /* Assert that MMU is turned off */ 74*1a92a0e0SAntonio Nino Diaz#if ENABLE_ASSERTIONS 75*1a92a0e0SAntonio Nino Diaz ldcopr r1, HSCTLR 76*1a92a0e0SAntonio Nino Diaz tst r1, #HSCTLR_M_BIT 77*1a92a0e0SAntonio Nino Diaz ASM_ASSERT(eq) 78*1a92a0e0SAntonio Nino Diaz#endif 79*1a92a0e0SAntonio Nino Diaz 80*1a92a0e0SAntonio Nino Diaz /* Invalidate TLB entries */ 81*1a92a0e0SAntonio Nino Diaz TLB_INVALIDATE(r0, TLBIALL) 82*1a92a0e0SAntonio Nino Diaz 83*1a92a0e0SAntonio Nino Diaz mov r3, r0 84*1a92a0e0SAntonio Nino Diaz ldr r0, =mmu_cfg_params 85*1a92a0e0SAntonio Nino Diaz 86*1a92a0e0SAntonio Nino Diaz /* HMAIR0 */ 87*1a92a0e0SAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_MAIR << 3)] 88*1a92a0e0SAntonio Nino Diaz stcopr r1, HMAIR0 89*1a92a0e0SAntonio Nino Diaz 90*1a92a0e0SAntonio Nino Diaz /* HTCR */ 91*1a92a0e0SAntonio Nino Diaz ldr r2, [r0, #(MMU_CFG_TCR << 3)] 92*1a92a0e0SAntonio Nino Diaz stcopr r2, HTCR 93*1a92a0e0SAntonio Nino Diaz 94*1a92a0e0SAntonio Nino Diaz /* HTTBR */ 95*1a92a0e0SAntonio Nino Diaz ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)] 96*1a92a0e0SAntonio Nino Diaz ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)] 97*1a92a0e0SAntonio Nino Diaz stcopr16 r1, r2, HTTBR_64 98*1a92a0e0SAntonio Nino Diaz 99*1a92a0e0SAntonio Nino Diaz /* 100*1a92a0e0SAntonio Nino Diaz * Ensure all translation table writes have drained into memory, the TLB 101*1a92a0e0SAntonio Nino Diaz * invalidation is complete, and translation register writes are 102*1a92a0e0SAntonio Nino Diaz * committed before enabling the MMU 103*1a92a0e0SAntonio Nino Diaz */ 104*1a92a0e0SAntonio Nino Diaz dsb ish 105*1a92a0e0SAntonio Nino Diaz isb 106*1a92a0e0SAntonio Nino Diaz 107*1a92a0e0SAntonio Nino Diaz /* Enable enable MMU by honoring flags */ 108*1a92a0e0SAntonio Nino Diaz ldcopr r1, HSCTLR 109*1a92a0e0SAntonio Nino Diaz ldr r2, =(HSCTLR_WXN_BIT | HSCTLR_C_BIT | HSCTLR_M_BIT) 110*1a92a0e0SAntonio Nino Diaz orr r1, r1, r2 111*1a92a0e0SAntonio Nino Diaz 112*1a92a0e0SAntonio Nino Diaz /* Clear C bit if requested */ 113*1a92a0e0SAntonio Nino Diaz tst r3, #DISABLE_DCACHE 114*1a92a0e0SAntonio Nino Diaz bicne r1, r1, #HSCTLR_C_BIT 115*1a92a0e0SAntonio Nino Diaz 116*1a92a0e0SAntonio Nino Diaz stcopr r1, HSCTLR 117*1a92a0e0SAntonio Nino Diaz isb 118*1a92a0e0SAntonio Nino Diaz 119*1a92a0e0SAntonio Nino Diaz bx lr 120*1a92a0e0SAntonio Nino Diazendfunc enable_mmu_direct_hyp 121