1*0cc7aa89SJeenu Viswambharan/* 2*0cc7aa89SJeenu Viswambharan * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*0cc7aa89SJeenu Viswambharan * 4*0cc7aa89SJeenu Viswambharan * SPDX-License-Identifier: BSD-3-Clause 5*0cc7aa89SJeenu Viswambharan */ 6*0cc7aa89SJeenu Viswambharan 7*0cc7aa89SJeenu Viswambharan#include <asm_macros.S> 8*0cc7aa89SJeenu Viswambharan#include <assert_macros.S> 9*0cc7aa89SJeenu Viswambharan#include <xlat_tables_v2.h> 10*0cc7aa89SJeenu Viswambharan 11*0cc7aa89SJeenu Viswambharan .global enable_mmu_direct 12*0cc7aa89SJeenu Viswambharan 13*0cc7aa89SJeenu Viswambharanfunc enable_mmu_direct 14*0cc7aa89SJeenu Viswambharan /* Assert that MMU is turned off */ 15*0cc7aa89SJeenu Viswambharan#if ENABLE_ASSERTIONS 16*0cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 17*0cc7aa89SJeenu Viswambharan tst r1, #SCTLR_M_BIT 18*0cc7aa89SJeenu Viswambharan ASM_ASSERT(eq) 19*0cc7aa89SJeenu Viswambharan#endif 20*0cc7aa89SJeenu Viswambharan 21*0cc7aa89SJeenu Viswambharan /* Invalidate TLB entries */ 22*0cc7aa89SJeenu Viswambharan TLB_INVALIDATE(r0, TLBIALL) 23*0cc7aa89SJeenu Viswambharan 24*0cc7aa89SJeenu Viswambharan mov r3, r0 25*0cc7aa89SJeenu Viswambharan ldr r0, =mmu_cfg_params 26*0cc7aa89SJeenu Viswambharan 27*0cc7aa89SJeenu Viswambharan /* MAIR0 */ 28*0cc7aa89SJeenu Viswambharan ldr r1, [r0, #(MMU_CFG_MAIR0 << 2)] 29*0cc7aa89SJeenu Viswambharan stcopr r1, MAIR0 30*0cc7aa89SJeenu Viswambharan 31*0cc7aa89SJeenu Viswambharan /* TTBCR */ 32*0cc7aa89SJeenu Viswambharan ldr r2, [r0, #(MMU_CFG_TCR << 2)] 33*0cc7aa89SJeenu Viswambharan stcopr r2, TTBCR 34*0cc7aa89SJeenu Viswambharan 35*0cc7aa89SJeenu Viswambharan /* TTBR0 */ 36*0cc7aa89SJeenu Viswambharan ldr r1, [r0, #(MMU_CFG_TTBR0_LO << 2)] 37*0cc7aa89SJeenu Viswambharan ldr r2, [r0, #(MMU_CFG_TTBR0_HI << 2)] 38*0cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR0_64 39*0cc7aa89SJeenu Viswambharan 40*0cc7aa89SJeenu Viswambharan /* TTBR1 is unused right now; set it to 0. */ 41*0cc7aa89SJeenu Viswambharan mov r1, #0 42*0cc7aa89SJeenu Viswambharan mov r2, #0 43*0cc7aa89SJeenu Viswambharan stcopr16 r1, r2, TTBR1_64 44*0cc7aa89SJeenu Viswambharan 45*0cc7aa89SJeenu Viswambharan /* 46*0cc7aa89SJeenu Viswambharan * Ensure all translation table writes have drained into memory, the TLB 47*0cc7aa89SJeenu Viswambharan * invalidation is complete, and translation register writes are 48*0cc7aa89SJeenu Viswambharan * committed before enabling the MMU 49*0cc7aa89SJeenu Viswambharan */ 50*0cc7aa89SJeenu Viswambharan dsb ish 51*0cc7aa89SJeenu Viswambharan isb 52*0cc7aa89SJeenu Viswambharan 53*0cc7aa89SJeenu Viswambharan /* Enable enable MMU by honoring flags */ 54*0cc7aa89SJeenu Viswambharan ldcopr r1, SCTLR 55*0cc7aa89SJeenu Viswambharan ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) 56*0cc7aa89SJeenu Viswambharan orr r1, r1, r2 57*0cc7aa89SJeenu Viswambharan 58*0cc7aa89SJeenu Viswambharan /* Clear C bit if requested */ 59*0cc7aa89SJeenu Viswambharan tst r3, #DISABLE_DCACHE 60*0cc7aa89SJeenu Viswambharan bicne r1, r1, #SCTLR_C_BIT 61*0cc7aa89SJeenu Viswambharan 62*0cc7aa89SJeenu Viswambharan stcopr r1, SCTLR 63*0cc7aa89SJeenu Viswambharan isb 64*0cc7aa89SJeenu Viswambharan 65*0cc7aa89SJeenu Viswambharan bx lr 66*0cc7aa89SJeenu Viswambharanendfunc enable_mmu_direct 67