13ca9928dSSoby Mathew /* 23ca9928dSSoby Mathew * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 33ca9928dSSoby Mathew * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53ca9928dSSoby Mathew */ 63ca9928dSSoby Mathew 73ca9928dSSoby Mathew #ifndef __XLAT_TABLES_PRIVATE_H__ 83ca9928dSSoby Mathew #define __XLAT_TABLES_PRIVATE_H__ 93ca9928dSSoby Mathew 10e8719552SAntonio Nino Diaz #include <cassert.h> 110029624fSAntonio Nino Diaz #include <platform_def.h> 1253d9c9c8SScott Branden #include <utils_def.h> 13e8719552SAntonio Nino Diaz 140029624fSAntonio Nino Diaz /* 150029624fSAntonio Nino Diaz * If the platform hasn't defined a physical and a virtual address space size 160029624fSAntonio Nino Diaz * default to ADDR_SPACE_SIZE. 170029624fSAntonio Nino Diaz */ 180029624fSAntonio Nino Diaz #if ERROR_DEPRECATED 190029624fSAntonio Nino Diaz # ifdef ADDR_SPACE_SIZE 200029624fSAntonio Nino Diaz # error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead." 210029624fSAntonio Nino Diaz # endif 220029624fSAntonio Nino Diaz #elif defined(ADDR_SPACE_SIZE) 230029624fSAntonio Nino Diaz # ifndef PLAT_PHY_ADDR_SPACE_SIZE 240029624fSAntonio Nino Diaz # define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE 250029624fSAntonio Nino Diaz # endif 260029624fSAntonio Nino Diaz # ifndef PLAT_VIRT_ADDR_SPACE_SIZE 270029624fSAntonio Nino Diaz # define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE 280029624fSAntonio Nino Diaz # endif 290029624fSAntonio Nino Diaz #endif 300029624fSAntonio Nino Diaz 310029624fSAntonio Nino Diaz /* The virtual and physical address space sizes must be powers of two. */ 320029624fSAntonio Nino Diaz CASSERT(IS_POWER_OF_TWO(PLAT_VIRT_ADDR_SPACE_SIZE), 330029624fSAntonio Nino Diaz assert_valid_virt_addr_space_size); 340029624fSAntonio Nino Diaz CASSERT(IS_POWER_OF_TWO(PLAT_PHY_ADDR_SPACE_SIZE), 350029624fSAntonio Nino Diaz assert_valid_phy_addr_space_size); 36e8719552SAntonio Nino Diaz 372240f45bSAntonio Nino Diaz /* 382240f45bSAntonio Nino Diaz * In AArch32 state, the MMU only supports 4KB page granularity, which means 392240f45bSAntonio Nino Diaz * that the first translation table level is either 1 or 2. Both of them are 402240f45bSAntonio Nino Diaz * allowed to have block and table descriptors. See section G4.5.6 of the 412240f45bSAntonio Nino Diaz * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. 422240f45bSAntonio Nino Diaz * 432240f45bSAntonio Nino Diaz * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page 442240f45bSAntonio Nino Diaz * granularity. For 4KB granularity, a level 0 table descriptor doesn't support 452240f45bSAntonio Nino Diaz * block translation. For 16KB, the same thing happens to levels 0 and 1. For 462240f45bSAntonio Nino Diaz * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture 472240f45bSAntonio Nino Diaz * Reference Manual (DDI 0487A.k) for more information. 482240f45bSAntonio Nino Diaz * 492240f45bSAntonio Nino Diaz * The define below specifies the first table level that allows block 502240f45bSAntonio Nino Diaz * descriptors. 512240f45bSAntonio Nino Diaz */ 522240f45bSAntonio Nino Diaz 532240f45bSAntonio Nino Diaz #ifdef AARCH32 542240f45bSAntonio Nino Diaz 552240f45bSAntonio Nino Diaz # define XLAT_BLOCK_LEVEL_MIN 1 562240f45bSAntonio Nino Diaz 572240f45bSAntonio Nino Diaz #else /* if AArch64 */ 582240f45bSAntonio Nino Diaz 592240f45bSAntonio Nino Diaz # if PAGE_SIZE == (4*1024) /* 4KB */ 602240f45bSAntonio Nino Diaz # define XLAT_BLOCK_LEVEL_MIN 1 612240f45bSAntonio Nino Diaz # else /* 16KB or 64KB */ 622240f45bSAntonio Nino Diaz # define XLAT_BLOCK_LEVEL_MIN 2 632240f45bSAntonio Nino Diaz # endif 642240f45bSAntonio Nino Diaz 652240f45bSAntonio Nino Diaz #endif /* AARCH32 */ 662240f45bSAntonio Nino Diaz 673ca9928dSSoby Mathew void print_mmap(void); 683ca9928dSSoby Mathew void init_xlation_table(uintptr_t base_va, uint64_t *table, 693ca9928dSSoby Mathew int level, uintptr_t *max_va, 703ca9928dSSoby Mathew unsigned long long *max_pa); 713ca9928dSSoby Mathew 723ca9928dSSoby Mathew #endif /* __XLAT_TABLES_PRIVATE_H__ */ 73