1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <cassert.h> 35 #include <platform_def.h> 36 #include <utils.h> 37 #include <xlat_tables.h> 38 #include "../xlat_tables_private.h" 39 40 /* 41 * The virtual address space size must be a power of two. As we start the initial 42 * lookup at level 1, it must also be between 2 GB and 4 GB. See section 43 * G4.6.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 44 * information. 45 */ 46 CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 32) && 47 IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size); 48 49 #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) 50 51 static uint64_t l1_xlation_table[NUM_L1_ENTRIES] 52 __aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); 53 54 void init_xlat_tables(void) 55 { 56 unsigned long long max_pa; 57 uintptr_t max_va; 58 print_mmap(); 59 init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa); 60 assert(max_va < ADDR_SPACE_SIZE); 61 } 62 63 /******************************************************************************* 64 * Function for enabling the MMU in Secure PL1, assuming that the 65 * page-tables have already been created. 66 ******************************************************************************/ 67 void enable_mmu_secure(unsigned int flags) 68 { 69 unsigned int mair0, ttbcr, sctlr; 70 uint64_t ttbr0; 71 72 assert(IS_IN_SECURE()); 73 assert((read_sctlr() & SCTLR_M_BIT) == 0); 74 75 /* Set attributes in the right indices of the MAIR */ 76 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 77 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 78 ATTR_IWBWA_OWBWA_NTR_INDEX); 79 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 80 ATTR_NON_CACHEABLE_INDEX); 81 write_mair0(mair0); 82 83 /* Invalidate TLBs at the current exception level */ 84 tlbiall(); 85 86 /* 87 * Set TTBCR bits as well. Set TTBR0 table properties as Inner 88 * & outer WBWA & shareable. Disable TTBR1. 89 */ 90 ttbcr = TTBCR_EAE_BIT | 91 TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 92 TTBCR_RGN0_INNER_WBA | 93 (32 - __builtin_ctzl((uintptr_t)ADDR_SPACE_SIZE)); 94 ttbcr |= TTBCR_EPD1_BIT; 95 write_ttbcr(ttbcr); 96 97 /* Set TTBR0 bits as well */ 98 ttbr0 = (uintptr_t) l1_xlation_table; 99 write64_ttbr0(ttbr0); 100 write64_ttbr1(0); 101 102 /* 103 * Ensure all translation table writes have drained 104 * into memory, the TLB invalidation is complete, 105 * and translation register writes are committed 106 * before enabling the MMU 107 */ 108 dsb(); 109 isb(); 110 111 sctlr = read_sctlr(); 112 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 113 114 if (flags & DISABLE_DCACHE) 115 sctlr &= ~SCTLR_C_BIT; 116 else 117 sctlr |= SCTLR_C_BIT; 118 119 write_sctlr(sctlr); 120 121 /* Ensure the MMU enable takes effect immediately */ 122 isb(); 123 } 124