1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <cassert.h> 35 #include <platform_def.h> 36 #include <utils.h> 37 #include <xlat_tables.h> 38 #include "../xlat_tables_private.h" 39 40 /* 41 * Each platform can define the size of the virtual address space, which is 42 * defined in ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus the width 43 * of said address space. The value of TTBCR.TxSZ must be in the range 0 to 44 * 7 [1], which means that the virtual address space width must be in the range 45 * 32 to 25 bits. 46 * 47 * Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE. 48 * For a 4 KB page size, level 1 supports virtual address spaces of widths 32 49 * to 31 bits, and level 2 from 30 to 25. Wider or narrower address spaces are 50 * not supported. As a result, level 3 cannot be used as initial lookup level 51 * with 4 KB granularity [1]. 52 * 53 * For example, for a 31-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 31), 54 * TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table G4-5 in 55 * the ARM ARM, the initial lookup level for such an address space is 1. 56 * 57 * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 58 * information: 59 * [1] Section G4.6.5 60 */ 61 62 #if ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN)) 63 64 # error "ADDR_SPACE_SIZE is too big." 65 66 #elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) 67 68 # define XLAT_TABLE_LEVEL_BASE 1 69 # define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) 70 71 #elif ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX)) 72 73 # define XLAT_TABLE_LEVEL_BASE 2 74 # define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) 75 76 #else 77 78 # error "ADDR_SPACE_SIZE is too small." 79 80 #endif 81 82 static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] 83 __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); 84 85 void init_xlat_tables(void) 86 { 87 unsigned long long max_pa; 88 uintptr_t max_va; 89 print_mmap(); 90 init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE, 91 &max_va, &max_pa); 92 assert(max_va < ADDR_SPACE_SIZE); 93 } 94 95 /******************************************************************************* 96 * Function for enabling the MMU in Secure PL1, assuming that the 97 * page-tables have already been created. 98 ******************************************************************************/ 99 void enable_mmu_secure(unsigned int flags) 100 { 101 unsigned int mair0, ttbcr, sctlr; 102 uint64_t ttbr0; 103 104 assert(IS_IN_SECURE()); 105 assert((read_sctlr() & SCTLR_M_BIT) == 0); 106 107 /* Set attributes in the right indices of the MAIR */ 108 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 109 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 110 ATTR_IWBWA_OWBWA_NTR_INDEX); 111 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 112 ATTR_NON_CACHEABLE_INDEX); 113 write_mair0(mair0); 114 115 /* Invalidate TLBs at the current exception level */ 116 tlbiall(); 117 118 /* 119 * Set TTBCR bits as well. Set TTBR0 table properties as Inner 120 * & outer WBWA & shareable. Disable TTBR1. 121 */ 122 ttbcr = TTBCR_EAE_BIT | 123 TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 124 TTBCR_RGN0_INNER_WBA | 125 (32 - __builtin_ctzl((uintptr_t)ADDR_SPACE_SIZE)); 126 ttbcr |= TTBCR_EPD1_BIT; 127 write_ttbcr(ttbcr); 128 129 /* Set TTBR0 bits as well */ 130 ttbr0 = (uintptr_t) base_xlation_table; 131 write64_ttbr0(ttbr0); 132 write64_ttbr1(0); 133 134 /* 135 * Ensure all translation table writes have drained 136 * into memory, the TLB invalidation is complete, 137 * and translation register writes are committed 138 * before enabling the MMU 139 */ 140 dsb(); 141 isb(); 142 143 sctlr = read_sctlr(); 144 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 145 146 if (flags & DISABLE_DCACHE) 147 sctlr &= ~SCTLR_C_BIT; 148 else 149 sctlr |= SCTLR_C_BIT; 150 151 write_sctlr(sctlr); 152 153 /* Ensure the MMU enable takes effect immediately */ 154 isb(); 155 } 156