1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <cpu_data.h> 14 #include <debug.h> 15 #include <platform.h> 16 #include <pmf.h> 17 #include <runtime_instr.h> 18 #include <stddef.h> 19 #include "psci_private.h" 20 21 /******************************************************************************* 22 * This function does generic and platform specific operations after a wake-up 23 * from standby/retention states at multiple power levels. 24 ******************************************************************************/ 25 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, 26 unsigned int end_pwrlvl) 27 { 28 psci_power_state_t state_info; 29 30 psci_acquire_pwr_domain_locks(end_pwrlvl, 31 cpu_idx); 32 33 /* 34 * Find out which retention states this CPU has exited from until the 35 * 'end_pwrlvl'. The exit retention state could be deeper than the entry 36 * state as a result of state coordination amongst other CPUs post wfi. 37 */ 38 psci_get_target_local_pwr_states(end_pwrlvl, &state_info); 39 40 #if ENABLE_PSCI_STAT 41 plat_psci_stat_accounting_stop(&state_info); 42 psci_stats_update_pwr_up(end_pwrlvl, &state_info); 43 #endif 44 45 /* 46 * Plat. management: Allow the platform to do operations 47 * on waking up from retention. 48 */ 49 psci_plat_pm_ops->pwr_domain_suspend_finish(&state_info); 50 51 /* 52 * Set the requested and target state of this CPU and all the higher 53 * power domain levels for this CPU to run. 54 */ 55 psci_set_pwr_domains_to_run(end_pwrlvl); 56 57 psci_release_pwr_domain_locks(end_pwrlvl, 58 cpu_idx); 59 } 60 61 /******************************************************************************* 62 * This function does generic and platform specific suspend to power down 63 * operations. 64 ******************************************************************************/ 65 static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, 66 entry_point_info_t *ep, 67 psci_power_state_t *state_info) 68 { 69 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); 70 71 /* Save PSCI target power level for the suspend finisher handler */ 72 psci_set_suspend_pwrlvl(end_pwrlvl); 73 74 /* 75 * Flush the target power level as it might be accessed on power up with 76 * Data cache disabled. 77 */ 78 psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 79 80 /* 81 * Call the cpu suspend handler registered by the Secure Payload 82 * Dispatcher to let it do any book-keeping. If the handler encounters an 83 * error, it's expected to assert within 84 */ 85 if (psci_spd_pm && psci_spd_pm->svc_suspend) 86 psci_spd_pm->svc_suspend(max_off_lvl); 87 88 #if !HW_ASSISTED_COHERENCY 89 /* 90 * Plat. management: Allow the platform to perform any early 91 * actions required to power down the CPU. This might be useful for 92 * HW_ASSISTED_COHERENCY = 0 platforms that can safely perform these 93 * actions with data caches enabled. 94 */ 95 if (psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early) 96 psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early(state_info); 97 #endif 98 99 /* 100 * Store the re-entry information for the non-secure world. 101 */ 102 cm_init_my_context(ep); 103 104 #if ENABLE_RUNTIME_INSTRUMENTATION 105 106 /* 107 * Flush cache line so that even if CPU power down happens 108 * the timestamp update is reflected in memory. 109 */ 110 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 111 RT_INSTR_ENTER_CFLUSH, 112 PMF_CACHE_MAINT); 113 #endif 114 115 /* 116 * Arch. management. Initiate power down sequence. 117 * TODO : Introduce a mechanism to query the cache level to flush 118 * and the cpu-ops power down to perform from the platform. 119 */ 120 psci_do_pwrdown_sequence(max_off_lvl); 121 122 #if ENABLE_RUNTIME_INSTRUMENTATION 123 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 124 RT_INSTR_EXIT_CFLUSH, 125 PMF_NO_CACHE_MAINT); 126 #endif 127 } 128 129 /******************************************************************************* 130 * Top level handler which is called when a cpu wants to suspend its execution. 131 * It is assumed that along with suspending the cpu power domain, power domains 132 * at higher levels until the target power level will be suspended as well. It 133 * coordinates with the platform to negotiate the target state for each of 134 * the power domain level till the target power domain level. It then performs 135 * generic, architectural, platform setup and state management required to 136 * suspend that power domain level and power domain levels below it. 137 * e.g. For a cpu that's to be suspended, it could mean programming the 138 * power controller whereas for a cluster that's to be suspended, it will call 139 * the platform specific code which will disable coherency at the interconnect 140 * level if the cpu is the last in the cluster and also the program the power 141 * controller. 142 * 143 * All the required parameter checks are performed at the beginning and after 144 * the state transition has been done, no further error is expected and it is 145 * not possible to undo any of the actions taken beyond that point. 146 ******************************************************************************/ 147 void psci_cpu_suspend_start(entry_point_info_t *ep, 148 unsigned int end_pwrlvl, 149 psci_power_state_t *state_info, 150 unsigned int is_power_down_state) 151 { 152 int skip_wfi = 0; 153 unsigned int idx = plat_my_core_pos(); 154 155 /* 156 * This function must only be called on platforms where the 157 * CPU_SUSPEND platform hooks have been implemented. 158 */ 159 assert(psci_plat_pm_ops->pwr_domain_suspend && 160 psci_plat_pm_ops->pwr_domain_suspend_finish); 161 162 /* 163 * This function acquires the lock corresponding to each power 164 * level so that by the time all locks are taken, the system topology 165 * is snapshot and state management can be done safely. 166 */ 167 psci_acquire_pwr_domain_locks(end_pwrlvl, 168 idx); 169 170 /* 171 * We check if there are any pending interrupts after the delay 172 * introduced by lock contention to increase the chances of early 173 * detection that a wake-up interrupt has fired. 174 */ 175 if (read_isr_el1()) { 176 skip_wfi = 1; 177 goto exit; 178 } 179 180 /* 181 * This function is passed the requested state info and 182 * it returns the negotiated state info for each power level upto 183 * the end level specified. 184 */ 185 psci_do_state_coordination(end_pwrlvl, state_info); 186 187 #if ENABLE_PSCI_STAT 188 /* Update the last cpu for each level till end_pwrlvl */ 189 psci_stats_update_pwr_down(end_pwrlvl, state_info); 190 #endif 191 192 if (is_power_down_state) 193 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); 194 195 /* 196 * Plat. management: Allow the platform to perform the 197 * necessary actions to turn off this cpu e.g. set the 198 * platform defined mailbox with the psci entrypoint, 199 * program the power controller etc. 200 */ 201 psci_plat_pm_ops->pwr_domain_suspend(state_info); 202 203 #if ENABLE_PSCI_STAT 204 plat_psci_stat_accounting_start(state_info); 205 #endif 206 207 exit: 208 /* 209 * Release the locks corresponding to each power level in the 210 * reverse order to which they were acquired. 211 */ 212 psci_release_pwr_domain_locks(end_pwrlvl, 213 idx); 214 if (skip_wfi) 215 return; 216 217 if (is_power_down_state) { 218 #if ENABLE_RUNTIME_INSTRUMENTATION 219 220 /* 221 * Update the timestamp with cache off. We assume this 222 * timestamp can only be read from the current CPU and the 223 * timestamp cache line will be flushed before return to 224 * normal world on wakeup. 225 */ 226 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 227 RT_INSTR_ENTER_HW_LOW_PWR, 228 PMF_NO_CACHE_MAINT); 229 #endif 230 231 /* The function calls below must not return */ 232 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) 233 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); 234 else 235 psci_power_down_wfi(); 236 } 237 238 #if ENABLE_RUNTIME_INSTRUMENTATION 239 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 240 RT_INSTR_ENTER_HW_LOW_PWR, 241 PMF_NO_CACHE_MAINT); 242 #endif 243 244 /* 245 * We will reach here if only retention/standby states have been 246 * requested at multiple power levels. This means that the cpu 247 * context will be preserved. 248 */ 249 wfi(); 250 251 #if ENABLE_RUNTIME_INSTRUMENTATION 252 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 253 RT_INSTR_EXIT_HW_LOW_PWR, 254 PMF_NO_CACHE_MAINT); 255 #endif 256 257 /* 258 * After we wake up from context retaining suspend, call the 259 * context retaining suspend finisher. 260 */ 261 psci_suspend_to_standby_finisher(idx, end_pwrlvl); 262 } 263 264 /******************************************************************************* 265 * The following functions finish an earlier suspend request. They 266 * are called by the common finisher routine in psci_common.c. The `state_info` 267 * is the psci_power_state from which this CPU has woken up from. 268 ******************************************************************************/ 269 void psci_cpu_suspend_finish(unsigned int cpu_idx, 270 psci_power_state_t *state_info) 271 { 272 unsigned int counter_freq; 273 unsigned int max_off_lvl; 274 275 /* Ensure we have been woken up from a suspended state */ 276 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ 277 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); 278 279 /* 280 * Plat. management: Perform the platform specific actions 281 * before we change the state of the cpu e.g. enabling the 282 * gic or zeroing the mailbox register. If anything goes 283 * wrong then assert as there is no way to recover from this 284 * situation. 285 */ 286 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 287 288 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 289 /* Arch. management: Enable the data cache, stack memory maintenance. */ 290 psci_do_pwrup_cache_maintenance(); 291 #endif 292 293 /* Re-init the cntfrq_el0 register */ 294 counter_freq = plat_get_syscnt_freq2(); 295 write_cntfrq_el0(counter_freq); 296 297 /* 298 * Call the cpu suspend finish handler registered by the Secure Payload 299 * Dispatcher to let it do any bookeeping. If the handler encounters an 300 * error, it's expected to assert within 301 */ 302 if (psci_spd_pm && psci_spd_pm->svc_suspend_finish) { 303 max_off_lvl = psci_find_max_off_lvl(state_info); 304 assert (max_off_lvl != PSCI_INVALID_PWR_LVL); 305 psci_spd_pm->svc_suspend_finish(max_off_lvl); 306 } 307 308 /* Invalidate the suspend level for the cpu */ 309 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); 310 311 /* 312 * Generic management: Now we just need to retrieve the 313 * information that we had stashed away during the suspend 314 * call to set this cpu on its way. 315 */ 316 cm_prepare_el3_exit(NON_SECURE); 317 } 318