1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <arch.h> 34 #include <arch_helpers.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <cpu_data.h> 38 #include <debug.h> 39 #include <platform.h> 40 #include <stddef.h> 41 #include "psci_private.h" 42 43 /******************************************************************************* 44 * This function does generic and platform specific operations after a wake-up 45 * from standby/retention states at multiple power levels. 46 ******************************************************************************/ 47 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, 48 unsigned int end_pwrlvl) 49 { 50 psci_power_state_t state_info; 51 52 psci_acquire_pwr_domain_locks(end_pwrlvl, 53 cpu_idx); 54 55 /* 56 * Find out which retention states this CPU has exited from until the 57 * 'end_pwrlvl'. The exit retention state could be deeper than the entry 58 * state as a result of state coordination amongst other CPUs post wfi. 59 */ 60 psci_get_target_local_pwr_states(end_pwrlvl, &state_info); 61 62 /* 63 * Plat. management: Allow the platform to do operations 64 * on waking up from retention. 65 */ 66 psci_plat_pm_ops->pwr_domain_suspend_finish(&state_info); 67 68 /* 69 * Set the requested and target state of this CPU and all the higher 70 * power domain levels for this CPU to run. 71 */ 72 psci_set_pwr_domains_to_run(end_pwrlvl); 73 74 psci_release_pwr_domain_locks(end_pwrlvl, 75 cpu_idx); 76 } 77 78 /******************************************************************************* 79 * This function does generic and platform specific suspend to power down 80 * operations. 81 ******************************************************************************/ 82 static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, 83 entry_point_info_t *ep, 84 psci_power_state_t *state_info) 85 { 86 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); 87 88 /* Save PSCI target power level for the suspend finisher handler */ 89 psci_set_suspend_pwrlvl(end_pwrlvl); 90 91 /* 92 * Flush the target power level as it will be accessed on power up with 93 * Data cache disabled. 94 */ 95 flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 96 97 /* 98 * Call the cpu suspend handler registered by the Secure Payload 99 * Dispatcher to let it do any book-keeping. If the handler encounters an 100 * error, it's expected to assert within 101 */ 102 if (psci_spd_pm && psci_spd_pm->svc_suspend) 103 psci_spd_pm->svc_suspend(max_off_lvl); 104 105 /* 106 * Store the re-entry information for the non-secure world. 107 */ 108 cm_init_my_context(ep); 109 110 /* 111 * Arch. management. Perform the necessary steps to flush all 112 * cpu caches. Currently we assume that the power level correspond 113 * the cache level. 114 * TODO : Introduce a mechanism to query the cache level to flush 115 * and the cpu-ops power down to perform from the platform. 116 */ 117 psci_do_pwrdown_cache_maintenance(max_off_lvl); 118 } 119 120 /******************************************************************************* 121 * Top level handler which is called when a cpu wants to suspend its execution. 122 * It is assumed that along with suspending the cpu power domain, power domains 123 * at higher levels until the target power level will be suspended as well. It 124 * coordinates with the platform to negotiate the target state for each of 125 * the power domain level till the target power domain level. It then performs 126 * generic, architectural, platform setup and state management required to 127 * suspend that power domain level and power domain levels below it. 128 * e.g. For a cpu that's to be suspended, it could mean programming the 129 * power controller whereas for a cluster that's to be suspended, it will call 130 * the platform specific code which will disable coherency at the interconnect 131 * level if the cpu is the last in the cluster and also the program the power 132 * controller. 133 * 134 * All the required parameter checks are performed at the beginning and after 135 * the state transition has been done, no further error is expected and it is 136 * not possible to undo any of the actions taken beyond that point. 137 ******************************************************************************/ 138 void psci_cpu_suspend_start(entry_point_info_t *ep, 139 unsigned int end_pwrlvl, 140 psci_power_state_t *state_info, 141 unsigned int is_power_down_state) 142 { 143 int skip_wfi = 0; 144 unsigned int idx = plat_my_core_pos(); 145 146 /* 147 * This function must only be called on platforms where the 148 * CPU_SUSPEND platform hooks have been implemented. 149 */ 150 assert(psci_plat_pm_ops->pwr_domain_suspend && 151 psci_plat_pm_ops->pwr_domain_suspend_finish); 152 153 /* 154 * This function acquires the lock corresponding to each power 155 * level so that by the time all locks are taken, the system topology 156 * is snapshot and state management can be done safely. 157 */ 158 psci_acquire_pwr_domain_locks(end_pwrlvl, 159 idx); 160 161 /* 162 * We check if there are any pending interrupts after the delay 163 * introduced by lock contention to increase the chances of early 164 * detection that a wake-up interrupt has fired. 165 */ 166 if (read_isr_el1()) { 167 skip_wfi = 1; 168 goto exit; 169 } 170 171 /* 172 * This function is passed the requested state info and 173 * it returns the negotiated state info for each power level upto 174 * the end level specified. 175 */ 176 psci_do_state_coordination(end_pwrlvl, state_info); 177 178 #if ENABLE_PSCI_STAT 179 /* Update the last cpu for each level till end_pwrlvl */ 180 psci_stats_update_pwr_down(end_pwrlvl, state_info); 181 #endif 182 183 if (is_power_down_state) 184 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); 185 186 /* 187 * Plat. management: Allow the platform to perform the 188 * necessary actions to turn off this cpu e.g. set the 189 * platform defined mailbox with the psci entrypoint, 190 * program the power controller etc. 191 */ 192 psci_plat_pm_ops->pwr_domain_suspend(state_info); 193 194 #if ENABLE_PSCI_STAT 195 /* 196 * Capture time-stamp while entering low power state. 197 * No cache maintenance needed because caches are off 198 * and writes are direct to main memory. 199 */ 200 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 201 PMF_NO_CACHE_MAINT); 202 #endif 203 204 exit: 205 /* 206 * Release the locks corresponding to each power level in the 207 * reverse order to which they were acquired. 208 */ 209 psci_release_pwr_domain_locks(end_pwrlvl, 210 idx); 211 if (skip_wfi) 212 return; 213 214 if (is_power_down_state) { 215 /* The function calls below must not return */ 216 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) 217 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); 218 else 219 psci_power_down_wfi(); 220 } 221 222 /* 223 * We will reach here if only retention/standby states have been 224 * requested at multiple power levels. This means that the cpu 225 * context will be preserved. 226 */ 227 wfi(); 228 229 /* 230 * After we wake up from context retaining suspend, call the 231 * context retaining suspend finisher. 232 */ 233 psci_suspend_to_standby_finisher(idx, end_pwrlvl); 234 } 235 236 /******************************************************************************* 237 * The following functions finish an earlier suspend request. They 238 * are called by the common finisher routine in psci_common.c. The `state_info` 239 * is the psci_power_state from which this CPU has woken up from. 240 ******************************************************************************/ 241 void psci_cpu_suspend_finish(unsigned int cpu_idx, 242 psci_power_state_t *state_info) 243 { 244 unsigned int counter_freq; 245 unsigned int max_off_lvl; 246 247 /* Ensure we have been woken up from a suspended state */ 248 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ 249 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); 250 251 /* 252 * Plat. management: Perform the platform specific actions 253 * before we change the state of the cpu e.g. enabling the 254 * gic or zeroing the mailbox register. If anything goes 255 * wrong then assert as there is no way to recover from this 256 * situation. 257 */ 258 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 259 260 /* 261 * Arch. management: Enable the data cache, manage stack memory and 262 * restore the stashed EL3 architectural context from the 'cpu_context' 263 * structure for this cpu. 264 */ 265 psci_do_pwrup_cache_maintenance(); 266 267 /* Re-init the cntfrq_el0 register */ 268 counter_freq = plat_get_syscnt_freq2(); 269 write_cntfrq_el0(counter_freq); 270 271 /* 272 * Call the cpu suspend finish handler registered by the Secure Payload 273 * Dispatcher to let it do any bookeeping. If the handler encounters an 274 * error, it's expected to assert within 275 */ 276 if (psci_spd_pm && psci_spd_pm->svc_suspend) { 277 max_off_lvl = psci_find_max_off_lvl(state_info); 278 assert (max_off_lvl != PSCI_INVALID_PWR_LVL); 279 psci_spd_pm->svc_suspend_finish(max_off_lvl); 280 } 281 282 /* Invalidate the suspend level for the cpu */ 283 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); 284 285 /* 286 * Generic management: Now we just need to retrieve the 287 * information that we had stashed away during the suspend 288 * call to set this cpu on its way. 289 */ 290 cm_prepare_el3_exit(NON_SECURE); 291 } 292