1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <arch.h> 34 #include <arch_helpers.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <cpu_data.h> 38 #include <debug.h> 39 #include <platform.h> 40 #include <runtime_svc.h> 41 #include <stddef.h> 42 #include "psci_private.h" 43 44 /******************************************************************************* 45 * This function does generic and platform specific operations after a wake-up 46 * from standby/retention states at multiple power levels. 47 ******************************************************************************/ 48 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, 49 psci_power_state_t *state_info, 50 unsigned int end_pwrlvl) 51 { 52 psci_acquire_pwr_domain_locks(end_pwrlvl, 53 cpu_idx); 54 55 /* 56 * Plat. management: Allow the platform to do operations 57 * on waking up from retention. 58 */ 59 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 60 61 /* 62 * Set the requested and target state of this CPU and all the higher 63 * power domain levels for this CPU to run. 64 */ 65 psci_set_pwr_domains_to_run(end_pwrlvl); 66 67 psci_release_pwr_domain_locks(end_pwrlvl, 68 cpu_idx); 69 } 70 71 /******************************************************************************* 72 * This function does generic and platform specific suspend to power down 73 * operations. 74 ******************************************************************************/ 75 static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, 76 entry_point_info_t *ep, 77 psci_power_state_t *state_info) 78 { 79 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); 80 81 /* Save PSCI target power level for the suspend finisher handler */ 82 psci_set_suspend_pwrlvl(end_pwrlvl); 83 84 /* 85 * Flush the target power level as it will be accessed on power up with 86 * Data cache disabled. 87 */ 88 flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 89 90 /* 91 * Call the cpu suspend handler registered by the Secure Payload 92 * Dispatcher to let it do any book-keeping. If the handler encounters an 93 * error, it's expected to assert within 94 */ 95 if (psci_spd_pm && psci_spd_pm->svc_suspend) 96 psci_spd_pm->svc_suspend(max_off_lvl); 97 98 /* 99 * Store the re-entry information for the non-secure world. 100 */ 101 cm_init_my_context(ep); 102 103 /* 104 * Arch. management. Perform the necessary steps to flush all 105 * cpu caches. Currently we assume that the power level correspond 106 * the cache level. 107 * TODO : Introduce a mechanism to query the cache level to flush 108 * and the cpu-ops power down to perform from the platform. 109 */ 110 psci_do_pwrdown_cache_maintenance(max_off_lvl); 111 } 112 113 /******************************************************************************* 114 * Top level handler which is called when a cpu wants to suspend its execution. 115 * It is assumed that along with suspending the cpu power domain, power domains 116 * at higher levels until the target power level will be suspended as well. It 117 * coordinates with the platform to negotiate the target state for each of 118 * the power domain level till the target power domain level. It then performs 119 * generic, architectural, platform setup and state management required to 120 * suspend that power domain level and power domain levels below it. 121 * e.g. For a cpu that's to be suspended, it could mean programming the 122 * power controller whereas for a cluster that's to be suspended, it will call 123 * the platform specific code which will disable coherency at the interconnect 124 * level if the cpu is the last in the cluster and also the program the power 125 * controller. 126 * 127 * All the required parameter checks are performed at the beginning and after 128 * the state transition has been done, no further error is expected and it is 129 * not possible to undo any of the actions taken beyond that point. 130 ******************************************************************************/ 131 void psci_cpu_suspend_start(entry_point_info_t *ep, 132 unsigned int end_pwrlvl, 133 psci_power_state_t *state_info, 134 unsigned int is_power_down_state) 135 { 136 int skip_wfi = 0; 137 unsigned int idx = plat_my_core_pos(); 138 139 /* 140 * This function must only be called on platforms where the 141 * CPU_SUSPEND platform hooks have been implemented. 142 */ 143 assert(psci_plat_pm_ops->pwr_domain_suspend && 144 psci_plat_pm_ops->pwr_domain_suspend_finish); 145 146 /* 147 * This function acquires the lock corresponding to each power 148 * level so that by the time all locks are taken, the system topology 149 * is snapshot and state management can be done safely. 150 */ 151 psci_acquire_pwr_domain_locks(end_pwrlvl, 152 idx); 153 154 /* 155 * We check if there are any pending interrupts after the delay 156 * introduced by lock contention to increase the chances of early 157 * detection that a wake-up interrupt has fired. 158 */ 159 if (read_isr_el1()) { 160 skip_wfi = 1; 161 goto exit; 162 } 163 164 /* 165 * This function is passed the requested state info and 166 * it returns the negotiated state info for each power level upto 167 * the end level specified. 168 */ 169 psci_do_state_coordination(end_pwrlvl, state_info); 170 171 #if ENABLE_PSCI_STAT 172 /* Update the last cpu for each level till end_pwrlvl */ 173 psci_stats_update_pwr_down(end_pwrlvl, state_info); 174 #endif 175 176 if (is_power_down_state) 177 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); 178 179 /* 180 * Plat. management: Allow the platform to perform the 181 * necessary actions to turn off this cpu e.g. set the 182 * platform defined mailbox with the psci entrypoint, 183 * program the power controller etc. 184 */ 185 psci_plat_pm_ops->pwr_domain_suspend(state_info); 186 187 #if ENABLE_PSCI_STAT 188 /* 189 * Capture time-stamp while entering low power state. 190 * No cache maintenance needed because caches are off 191 * and writes are direct to main memory. 192 */ 193 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 194 PMF_NO_CACHE_MAINT); 195 #endif 196 197 exit: 198 /* 199 * Release the locks corresponding to each power level in the 200 * reverse order to which they were acquired. 201 */ 202 psci_release_pwr_domain_locks(end_pwrlvl, 203 idx); 204 if (skip_wfi) 205 return; 206 207 if (is_power_down_state) { 208 /* The function calls below must not return */ 209 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) 210 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); 211 else 212 psci_power_down_wfi(); 213 } 214 215 /* 216 * We will reach here if only retention/standby states have been 217 * requested at multiple power levels. This means that the cpu 218 * context will be preserved. 219 */ 220 wfi(); 221 222 /* 223 * After we wake up from context retaining suspend, call the 224 * context retaining suspend finisher. 225 */ 226 psci_suspend_to_standby_finisher(idx, state_info, end_pwrlvl); 227 } 228 229 /******************************************************************************* 230 * The following functions finish an earlier suspend request. They 231 * are called by the common finisher routine in psci_common.c. The `state_info` 232 * is the psci_power_state from which this CPU has woken up from. 233 ******************************************************************************/ 234 void psci_cpu_suspend_finish(unsigned int cpu_idx, 235 psci_power_state_t *state_info) 236 { 237 unsigned int counter_freq; 238 unsigned int max_off_lvl; 239 240 /* Ensure we have been woken up from a suspended state */ 241 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ 242 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); 243 244 /* 245 * Plat. management: Perform the platform specific actions 246 * before we change the state of the cpu e.g. enabling the 247 * gic or zeroing the mailbox register. If anything goes 248 * wrong then assert as there is no way to recover from this 249 * situation. 250 */ 251 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 252 253 /* 254 * Arch. management: Enable the data cache, manage stack memory and 255 * restore the stashed EL3 architectural context from the 'cpu_context' 256 * structure for this cpu. 257 */ 258 psci_do_pwrup_cache_maintenance(); 259 260 /* Re-init the cntfrq_el0 register */ 261 counter_freq = plat_get_syscnt_freq2(); 262 write_cntfrq_el0(counter_freq); 263 264 /* 265 * Call the cpu suspend finish handler registered by the Secure Payload 266 * Dispatcher to let it do any bookeeping. If the handler encounters an 267 * error, it's expected to assert within 268 */ 269 if (psci_spd_pm && psci_spd_pm->svc_suspend) { 270 max_off_lvl = psci_find_max_off_lvl(state_info); 271 assert (max_off_lvl != PSCI_INVALID_PWR_LVL); 272 psci_spd_pm->svc_suspend_finish(max_off_lvl); 273 } 274 275 /* Invalidate the suspend level for the cpu */ 276 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); 277 278 /* 279 * Generic management: Now we just need to retrieve the 280 * information that we had stashed away during the suspend 281 * call to set this cpu on its way. 282 */ 283 cm_prepare_el3_exit(NON_SECURE); 284 } 285