1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <arch.h> 34 #include <arch_helpers.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <cpu_data.h> 38 #include <debug.h> 39 #include <platform.h> 40 #include <stddef.h> 41 #include "psci_private.h" 42 43 /******************************************************************************* 44 * This function does generic and platform specific operations after a wake-up 45 * from standby/retention states at multiple power levels. 46 ******************************************************************************/ 47 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, 48 psci_power_state_t *state_info, 49 unsigned int end_pwrlvl) 50 { 51 psci_acquire_pwr_domain_locks(end_pwrlvl, 52 cpu_idx); 53 54 /* 55 * Plat. management: Allow the platform to do operations 56 * on waking up from retention. 57 */ 58 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 59 60 /* 61 * Set the requested and target state of this CPU and all the higher 62 * power domain levels for this CPU to run. 63 */ 64 psci_set_pwr_domains_to_run(end_pwrlvl); 65 66 psci_release_pwr_domain_locks(end_pwrlvl, 67 cpu_idx); 68 } 69 70 /******************************************************************************* 71 * This function does generic and platform specific suspend to power down 72 * operations. 73 ******************************************************************************/ 74 static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, 75 entry_point_info_t *ep, 76 psci_power_state_t *state_info) 77 { 78 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); 79 80 /* Save PSCI target power level for the suspend finisher handler */ 81 psci_set_suspend_pwrlvl(end_pwrlvl); 82 83 /* 84 * Flush the target power level as it will be accessed on power up with 85 * Data cache disabled. 86 */ 87 flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 88 89 /* 90 * Call the cpu suspend handler registered by the Secure Payload 91 * Dispatcher to let it do any book-keeping. If the handler encounters an 92 * error, it's expected to assert within 93 */ 94 if (psci_spd_pm && psci_spd_pm->svc_suspend) 95 psci_spd_pm->svc_suspend(max_off_lvl); 96 97 /* 98 * Store the re-entry information for the non-secure world. 99 */ 100 cm_init_my_context(ep); 101 102 /* 103 * Arch. management. Perform the necessary steps to flush all 104 * cpu caches. Currently we assume that the power level correspond 105 * the cache level. 106 * TODO : Introduce a mechanism to query the cache level to flush 107 * and the cpu-ops power down to perform from the platform. 108 */ 109 psci_do_pwrdown_cache_maintenance(max_off_lvl); 110 } 111 112 /******************************************************************************* 113 * Top level handler which is called when a cpu wants to suspend its execution. 114 * It is assumed that along with suspending the cpu power domain, power domains 115 * at higher levels until the target power level will be suspended as well. It 116 * coordinates with the platform to negotiate the target state for each of 117 * the power domain level till the target power domain level. It then performs 118 * generic, architectural, platform setup and state management required to 119 * suspend that power domain level and power domain levels below it. 120 * e.g. For a cpu that's to be suspended, it could mean programming the 121 * power controller whereas for a cluster that's to be suspended, it will call 122 * the platform specific code which will disable coherency at the interconnect 123 * level if the cpu is the last in the cluster and also the program the power 124 * controller. 125 * 126 * All the required parameter checks are performed at the beginning and after 127 * the state transition has been done, no further error is expected and it is 128 * not possible to undo any of the actions taken beyond that point. 129 ******************************************************************************/ 130 void psci_cpu_suspend_start(entry_point_info_t *ep, 131 unsigned int end_pwrlvl, 132 psci_power_state_t *state_info, 133 unsigned int is_power_down_state) 134 { 135 int skip_wfi = 0; 136 unsigned int idx = plat_my_core_pos(); 137 138 /* 139 * This function must only be called on platforms where the 140 * CPU_SUSPEND platform hooks have been implemented. 141 */ 142 assert(psci_plat_pm_ops->pwr_domain_suspend && 143 psci_plat_pm_ops->pwr_domain_suspend_finish); 144 145 /* 146 * This function acquires the lock corresponding to each power 147 * level so that by the time all locks are taken, the system topology 148 * is snapshot and state management can be done safely. 149 */ 150 psci_acquire_pwr_domain_locks(end_pwrlvl, 151 idx); 152 153 /* 154 * We check if there are any pending interrupts after the delay 155 * introduced by lock contention to increase the chances of early 156 * detection that a wake-up interrupt has fired. 157 */ 158 if (read_isr_el1()) { 159 skip_wfi = 1; 160 goto exit; 161 } 162 163 /* 164 * This function is passed the requested state info and 165 * it returns the negotiated state info for each power level upto 166 * the end level specified. 167 */ 168 psci_do_state_coordination(end_pwrlvl, state_info); 169 170 #if ENABLE_PSCI_STAT 171 /* Update the last cpu for each level till end_pwrlvl */ 172 psci_stats_update_pwr_down(end_pwrlvl, state_info); 173 #endif 174 175 if (is_power_down_state) 176 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); 177 178 /* 179 * Plat. management: Allow the platform to perform the 180 * necessary actions to turn off this cpu e.g. set the 181 * platform defined mailbox with the psci entrypoint, 182 * program the power controller etc. 183 */ 184 psci_plat_pm_ops->pwr_domain_suspend(state_info); 185 186 #if ENABLE_PSCI_STAT 187 /* 188 * Capture time-stamp while entering low power state. 189 * No cache maintenance needed because caches are off 190 * and writes are direct to main memory. 191 */ 192 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, 193 PMF_NO_CACHE_MAINT); 194 #endif 195 196 exit: 197 /* 198 * Release the locks corresponding to each power level in the 199 * reverse order to which they were acquired. 200 */ 201 psci_release_pwr_domain_locks(end_pwrlvl, 202 idx); 203 if (skip_wfi) 204 return; 205 206 if (is_power_down_state) { 207 /* The function calls below must not return */ 208 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) 209 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); 210 else 211 psci_power_down_wfi(); 212 } 213 214 /* 215 * We will reach here if only retention/standby states have been 216 * requested at multiple power levels. This means that the cpu 217 * context will be preserved. 218 */ 219 wfi(); 220 221 /* 222 * After we wake up from context retaining suspend, call the 223 * context retaining suspend finisher. 224 */ 225 psci_suspend_to_standby_finisher(idx, state_info, end_pwrlvl); 226 } 227 228 /******************************************************************************* 229 * The following functions finish an earlier suspend request. They 230 * are called by the common finisher routine in psci_common.c. The `state_info` 231 * is the psci_power_state from which this CPU has woken up from. 232 ******************************************************************************/ 233 void psci_cpu_suspend_finish(unsigned int cpu_idx, 234 psci_power_state_t *state_info) 235 { 236 unsigned int counter_freq; 237 unsigned int max_off_lvl; 238 239 /* Ensure we have been woken up from a suspended state */ 240 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ 241 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); 242 243 /* 244 * Plat. management: Perform the platform specific actions 245 * before we change the state of the cpu e.g. enabling the 246 * gic or zeroing the mailbox register. If anything goes 247 * wrong then assert as there is no way to recover from this 248 * situation. 249 */ 250 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 251 252 /* 253 * Arch. management: Enable the data cache, manage stack memory and 254 * restore the stashed EL3 architectural context from the 'cpu_context' 255 * structure for this cpu. 256 */ 257 psci_do_pwrup_cache_maintenance(); 258 259 /* Re-init the cntfrq_el0 register */ 260 counter_freq = plat_get_syscnt_freq2(); 261 write_cntfrq_el0(counter_freq); 262 263 /* 264 * Call the cpu suspend finish handler registered by the Secure Payload 265 * Dispatcher to let it do any bookeeping. If the handler encounters an 266 * error, it's expected to assert within 267 */ 268 if (psci_spd_pm && psci_spd_pm->svc_suspend) { 269 max_off_lvl = psci_find_max_off_lvl(state_info); 270 assert (max_off_lvl != PSCI_INVALID_PWR_LVL); 271 psci_spd_pm->svc_suspend_finish(max_off_lvl); 272 } 273 274 /* Invalidate the suspend level for the cpu */ 275 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); 276 277 /* 278 * Generic management: Now we just need to retrieve the 279 * information that we had stashed away during the suspend 280 * call to set this cpu on its way. 281 */ 282 cm_prepare_el3_exit(NON_SECURE); 283 } 284