1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <debug.h> 9 #include <platform.h> 10 #include <platform_def.h> 11 #include "psci_private.h" 12 13 #ifndef PLAT_MAX_PWR_LVL_STATES 14 #define PLAT_MAX_PWR_LVL_STATES 2 15 #endif 16 17 /* Following structure is used for PSCI STAT */ 18 typedef struct psci_stat { 19 u_register_t residency; 20 u_register_t count; 21 } psci_stat_t; 22 23 /* 24 * Following is used to keep track of the last cpu 25 * that goes to power down in non cpu power domains. 26 */ 27 static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = { 28 [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1}; 29 30 /* 31 * Following are used to store PSCI STAT values for 32 * CPU and non CPU power domains. 33 */ 34 static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT] 35 [PLAT_MAX_PWR_LVL_STATES]; 36 static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS] 37 [PLAT_MAX_PWR_LVL_STATES]; 38 39 /* 40 * This functions returns the index into the `psci_stat_t` array given the 41 * local power state and power domain level. If the platform implements the 42 * `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index. 43 */ 44 static int get_stat_idx(plat_local_state_t local_state, int pwr_lvl) 45 { 46 int idx; 47 48 if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) { 49 assert(PLAT_MAX_PWR_LVL_STATES == 2); 50 if (is_local_state_retn(local_state)) 51 return 0; 52 53 assert(is_local_state_off(local_state)); 54 return 1; 55 } 56 57 idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl); 58 assert((idx >= 0) && (idx < PLAT_MAX_PWR_LVL_STATES)); 59 return idx; 60 } 61 62 /******************************************************************************* 63 * This function is passed the target local power states for each power 64 * domain (state_info) between the current CPU domain and its ancestors until 65 * the target power level (end_pwrlvl). 66 * 67 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 68 * updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id. 69 * 70 * This function will only be invoked with data cache enabled and while 71 * powering down a core. 72 ******************************************************************************/ 73 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 74 const psci_power_state_t *state_info) 75 { 76 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); 77 78 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 79 assert(state_info); 80 81 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 82 83 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 84 85 /* Break early if the target power state is RUN */ 86 if (is_local_state_run(state_info->pwr_domain_state[lvl])) 87 break; 88 89 /* 90 * The power domain is entering a low power state, so this is 91 * the last CPU for this power domain 92 */ 93 last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx; 94 95 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 96 } 97 98 } 99 100 /******************************************************************************* 101 * This function updates the PSCI STATS(residency time and count) for CPU 102 * and NON-CPU power domains. 103 * It is called with caches enabled and locks acquired(for NON-CPU domain) 104 ******************************************************************************/ 105 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 106 const psci_power_state_t *state_info) 107 { 108 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); 109 int stat_idx; 110 plat_local_state_t local_state; 111 u_register_t residency; 112 113 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 114 assert(state_info); 115 116 /* Get the index into the stats array */ 117 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; 118 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); 119 120 /* Call into platform interface to calculate residency. */ 121 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, 122 state_info, cpu_idx); 123 124 /* Update CPU stats. */ 125 psci_cpu_stat[cpu_idx][stat_idx].residency += residency; 126 psci_cpu_stat[cpu_idx][stat_idx].count++; 127 128 /* 129 * Check what power domains above CPU were off 130 * prior to this CPU powering on. 131 */ 132 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 133 /* Return early if this is the first power up. */ 134 if (last_cpu_in_non_cpu_pd[parent_idx] == -1) 135 return; 136 137 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 138 local_state = state_info->pwr_domain_state[lvl]; 139 if (is_local_state_run(local_state)) { 140 /* Break early */ 141 break; 142 } 143 144 assert(last_cpu_in_non_cpu_pd[parent_idx] != -1); 145 146 /* Call into platform interface to calculate residency. */ 147 residency = plat_psci_stat_get_residency(lvl, state_info, 148 last_cpu_in_non_cpu_pd[parent_idx]); 149 150 /* Initialize back to reset value */ 151 last_cpu_in_non_cpu_pd[parent_idx] = -1; 152 153 /* Get the index into the stats array */ 154 stat_idx = get_stat_idx(local_state, lvl); 155 156 /* Update non cpu stats */ 157 psci_non_cpu_stat[parent_idx][stat_idx].residency += residency; 158 psci_non_cpu_stat[parent_idx][stat_idx].count++; 159 160 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 161 } 162 163 } 164 165 /******************************************************************************* 166 * This function returns the appropriate count and residency time of the 167 * local state for the highest power level expressed in the `power_state` 168 * for the node represented by `target_cpu`. 169 ******************************************************************************/ 170 static int psci_get_stat(u_register_t target_cpu, unsigned int power_state, 171 psci_stat_t *psci_stat) 172 { 173 int rc; 174 unsigned int pwrlvl, lvl, parent_idx, stat_idx, target_idx; 175 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 176 plat_local_state_t local_state; 177 178 /* Validate the target_cpu parameter and determine the cpu index */ 179 target_idx = plat_core_pos_by_mpidr(target_cpu); 180 if (target_idx == -1) 181 return PSCI_E_INVALID_PARAMS; 182 183 /* Validate the power_state parameter */ 184 if (!psci_plat_pm_ops->translate_power_state_by_mpidr) 185 rc = psci_validate_power_state(power_state, &state_info); 186 else 187 rc = psci_plat_pm_ops->translate_power_state_by_mpidr( 188 target_cpu, power_state, &state_info); 189 190 if (rc != PSCI_E_SUCCESS) 191 return PSCI_E_INVALID_PARAMS; 192 193 /* Find the highest power level */ 194 pwrlvl = psci_find_target_suspend_lvl(&state_info); 195 if (pwrlvl == PSCI_INVALID_PWR_LVL) { 196 ERROR("Invalid target power level for PSCI statistics operation\n"); 197 panic(); 198 } 199 200 /* Get the index into the stats array */ 201 local_state = state_info.pwr_domain_state[pwrlvl]; 202 stat_idx = get_stat_idx(local_state, pwrlvl); 203 204 if (pwrlvl > PSCI_CPU_PWR_LVL) { 205 /* Get the power domain index */ 206 parent_idx = psci_cpu_pd_nodes[target_idx].parent_node; 207 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl < pwrlvl; lvl++) 208 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 209 210 /* Get the non cpu power domain stats */ 211 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx]; 212 } else { 213 /* Get the cpu power domain stats */ 214 *psci_stat = psci_cpu_stat[target_idx][stat_idx]; 215 } 216 217 return PSCI_E_SUCCESS; 218 } 219 220 /* This is the top level function for PSCI_STAT_RESIDENCY SMC. */ 221 u_register_t psci_stat_residency(u_register_t target_cpu, 222 unsigned int power_state) 223 { 224 psci_stat_t psci_stat; 225 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 226 227 if (rc == PSCI_E_SUCCESS) 228 return psci_stat.residency; 229 else 230 return 0; 231 } 232 233 /* This is the top level function for PSCI_STAT_COUNT SMC. */ 234 u_register_t psci_stat_count(u_register_t target_cpu, 235 unsigned int power_state) 236 { 237 psci_stat_t psci_stat; 238 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); 239 240 if (rc == PSCI_E_SUCCESS) 241 return psci_stat.count; 242 else 243 return 0; 244 } 245