1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <lib/cpus/errata_report.h> 16 #include <plat/common/platform.h> 17 18 #include "psci_private.h" 19 20 /******************************************************************************* 21 * Per cpu non-secure contexts used to program the architectural state prior 22 * return to the normal world. 23 * TODO: Use the memory allocator to set aside memory for the contexts instead 24 * of relying on platform defined constants. 25 ******************************************************************************/ 26 static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; 27 28 /****************************************************************************** 29 * Define the psci capability variable. 30 *****************************************************************************/ 31 unsigned int psci_caps; 32 33 /******************************************************************************* 34 * Function which initializes the 'psci_non_cpu_pd_nodes' or the 35 * 'psci_cpu_pd_nodes' corresponding to the power level. 36 ******************************************************************************/ 37 static void __init psci_init_pwr_domain_node(unsigned char node_idx, 38 unsigned int parent_idx, 39 unsigned char level) 40 { 41 if (level > PSCI_CPU_PWR_LVL) { 42 psci_non_cpu_pd_nodes[node_idx].level = level; 43 psci_lock_init(psci_non_cpu_pd_nodes, node_idx); 44 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; 45 psci_non_cpu_pd_nodes[node_idx].local_state = 46 PLAT_MAX_OFF_STATE; 47 } else { 48 psci_cpu_data_t *svc_cpu_data; 49 50 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; 51 52 /* Initialize with an invalid mpidr */ 53 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; 54 55 svc_cpu_data = 56 &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data); 57 58 /* Set the Affinity Info for the cores as OFF */ 59 svc_cpu_data->aff_info_state = AFF_STATE_OFF; 60 61 /* Invalidate the suspend level for the cpu */ 62 svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL; 63 64 /* Set the power state to OFF state */ 65 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; 66 67 psci_flush_dcache_range((uintptr_t)svc_cpu_data, 68 sizeof(*svc_cpu_data)); 69 70 cm_set_context_by_index(node_idx, 71 (void *) &psci_ns_context[node_idx], 72 NON_SECURE); 73 } 74 } 75 76 /******************************************************************************* 77 * This functions updates cpu_start_idx and ncpus field for each of the node in 78 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of 79 * the CPUs and check whether they match with the parent of the previous 80 * CPU. The basic assumption for this work is that children of the same parent 81 * are allocated adjacent indices. The platform should ensure this though proper 82 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and 83 * plat_my_core_pos() APIs. 84 *******************************************************************************/ 85 static void __init psci_update_pwrlvl_limits(void) 86 { 87 int j, cpu_idx; 88 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; 89 unsigned int temp_index[PLAT_MAX_PWR_LVL]; 90 91 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { 92 psci_get_parent_pwr_domain_nodes(cpu_idx, 93 (unsigned int)PLAT_MAX_PWR_LVL, 94 temp_index); 95 for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { 96 if (temp_index[j] != nodes_idx[j]) { 97 nodes_idx[j] = temp_index[j]; 98 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx 99 = cpu_idx; 100 } 101 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; 102 } 103 } 104 } 105 106 /******************************************************************************* 107 * Core routine to populate the power domain tree. The tree descriptor passed by 108 * the platform is populated breadth-first and the first entry in the map 109 * informs the number of root power domains. The parent nodes of the root nodes 110 * will point to an invalid entry(-1). 111 ******************************************************************************/ 112 static void __init populate_power_domain_tree(const unsigned char *topology) 113 { 114 unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; 115 unsigned int node_index = 0U, num_children; 116 int parent_node_index = 0; 117 int level = (int) PLAT_MAX_PWR_LVL; 118 119 /* 120 * For each level the inputs are: 121 * - number of nodes at this level in plat_array i.e. num_nodes_at_level 122 * This is the sum of values of nodes at the parent level. 123 * - Index of first entry at this level in the plat_array i.e. 124 * parent_node_index. 125 * - Index of first free entry in psci_non_cpu_pd_nodes[] or 126 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. 127 */ 128 while (level >= (int) PSCI_CPU_PWR_LVL) { 129 num_nodes_at_next_lvl = 0U; 130 /* 131 * For each entry (parent node) at this level in the plat_array: 132 * - Find the number of children 133 * - Allocate a node in a power domain array for each child 134 * - Set the parent of the child to the parent_node_index - 1 135 * - Increment parent_node_index to point to the next parent 136 * - Accumulate the number of children at next level. 137 */ 138 for (i = 0U; i < num_nodes_at_lvl; i++) { 139 assert(parent_node_index <= 140 PSCI_NUM_NON_CPU_PWR_DOMAINS); 141 num_children = topology[parent_node_index]; 142 143 for (j = node_index; 144 j < (node_index + num_children); j++) 145 psci_init_pwr_domain_node((unsigned char)j, 146 parent_node_index - 1, 147 (unsigned char)level); 148 149 node_index = j; 150 num_nodes_at_next_lvl += num_children; 151 parent_node_index++; 152 } 153 154 num_nodes_at_lvl = num_nodes_at_next_lvl; 155 level--; 156 157 /* Reset the index for the cpu power domain array */ 158 if (level == (int) PSCI_CPU_PWR_LVL) 159 node_index = 0; 160 } 161 162 /* Validate the sanity of array exported by the platform */ 163 assert((int) j == PLATFORM_CORE_COUNT); 164 } 165 166 /******************************************************************************* 167 * This function does the architectural setup and takes the warm boot 168 * entry-point `mailbox_ep` as an argument. The function also initializes the 169 * power domain topology tree by querying the platform. The power domain nodes 170 * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and 171 * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform 172 * exports its static topology map through the 173 * populate_power_domain_topology_tree() API. The algorithm populates the 174 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this 175 * topology map. On a platform that implements two clusters of 2 cpus each, 176 * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would 177 * look like this: 178 * 179 * --------------------------------------------------- 180 * | system node | cluster 0 node | cluster 1 node | 181 * --------------------------------------------------- 182 * 183 * And populated psci_cpu_pd_nodes would look like this : 184 * <- cpus cluster0 -><- cpus cluster1 -> 185 * ------------------------------------------------ 186 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | 187 * ------------------------------------------------ 188 ******************************************************************************/ 189 int __init psci_setup(const psci_lib_args_t *lib_args) 190 { 191 const unsigned char *topology_tree; 192 193 assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args)); 194 195 /* Do the Architectural initialization */ 196 psci_arch_setup(); 197 198 /* Query the topology map from the platform */ 199 topology_tree = plat_get_power_domain_tree_desc(); 200 201 /* Populate the power domain arrays using the platform topology map */ 202 populate_power_domain_tree(topology_tree); 203 204 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ 205 psci_update_pwrlvl_limits(); 206 207 /* Populate the mpidr field of cpu node for this CPU */ 208 psci_cpu_pd_nodes[plat_my_core_pos()].mpidr = 209 read_mpidr() & MPIDR_AFFINITY_MASK; 210 211 psci_init_req_local_pwr_states(); 212 213 /* 214 * Set the requested and target state of this CPU and all the higher 215 * power domain levels for this CPU to run. 216 */ 217 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); 218 219 (void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, 220 &psci_plat_pm_ops); 221 assert(psci_plat_pm_ops != NULL); 222 223 /* 224 * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs 225 * during warm boot, possibly before data cache is enabled. 226 */ 227 psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops, 228 sizeof(psci_plat_pm_ops)); 229 230 /* Initialize the psci capability */ 231 psci_caps = PSCI_GENERIC_CAP; 232 233 if (psci_plat_pm_ops->pwr_domain_off != NULL) 234 psci_caps |= define_psci_cap(PSCI_CPU_OFF); 235 if ((psci_plat_pm_ops->pwr_domain_on != NULL) && 236 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) 237 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); 238 if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) && 239 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) { 240 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); 241 if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) 242 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); 243 } 244 if (psci_plat_pm_ops->system_off != NULL) 245 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); 246 if (psci_plat_pm_ops->system_reset != NULL) 247 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); 248 if (psci_plat_pm_ops->get_node_hw_state != NULL) 249 psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64); 250 if ((psci_plat_pm_ops->read_mem_protect != NULL) && 251 (psci_plat_pm_ops->write_mem_protect != NULL)) 252 psci_caps |= define_psci_cap(PSCI_MEM_PROTECT); 253 if (psci_plat_pm_ops->mem_protect_chk != NULL) 254 psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64); 255 if (psci_plat_pm_ops->system_reset2 != NULL) 256 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64); 257 258 #if ENABLE_PSCI_STAT 259 psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64); 260 psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64); 261 #endif 262 263 return 0; 264 } 265 266 /******************************************************************************* 267 * This duplicates what the primary cpu did after a cold boot in BL1. The same 268 * needs to be done when a cpu is hotplugged in. This function could also over- 269 * ride any EL3 setup done by BL1 as this code resides in rw memory. 270 ******************************************************************************/ 271 void psci_arch_setup(void) 272 { 273 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) 274 /* Program the counter frequency */ 275 write_cntfrq_el0(plat_get_syscnt_freq2()); 276 #endif 277 278 /* Initialize the cpu_ops pointer. */ 279 init_cpu_ops(); 280 281 /* Having initialized cpu_ops, we can now print errata status */ 282 print_errata_status(); 283 284 #if ENABLE_PAUTH 285 /* Store APIAKey_EL1 key */ 286 set_cpu_data(apiakey[0], read_apiakeylo_el1()); 287 set_cpu_data(apiakey[1], read_apiakeyhi_el1()); 288 #endif /* ENABLE_PAUTH */ 289 } 290 291 /****************************************************************************** 292 * PSCI Library interface to initialize the cpu context for the next non 293 * secure image during cold boot. The relevant registers in the cpu context 294 * need to be retrieved and programmed on return from this interface. 295 *****************************************************************************/ 296 void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info) 297 { 298 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); 299 cm_init_my_context(next_image_info); 300 cm_prepare_el3_exit(NON_SECURE); 301 } 302