1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <context.h> 14 #include <lib/cpus/errata.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <plat/common/platform.h> 17 18 #include "psci_private.h" 19 20 /* 21 * Check that PLATFORM_CORE_COUNT fits into the number of cores 22 * that can be represented by PSCI_MAX_CPUS_INDEX. 23 */ 24 CASSERT(PLATFORM_CORE_COUNT <= (PSCI_MAX_CPUS_INDEX + 1U), assert_psci_cores_overflow); 25 26 /******************************************************************************* 27 * Per cpu non-secure contexts used to program the architectural state prior 28 * return to the normal world. 29 * TODO: Use the memory allocator to set aside memory for the contexts instead 30 * of relying on platform defined constants. 31 ******************************************************************************/ 32 static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; 33 static entry_point_info_t warmboot_ep_info[PLATFORM_CORE_COUNT]; 34 35 /****************************************************************************** 36 * Define the psci capability variable. 37 *****************************************************************************/ 38 unsigned int psci_caps; 39 40 /******************************************************************************* 41 * Function which initializes the 'psci_non_cpu_pd_nodes' or the 42 * 'psci_cpu_pd_nodes' corresponding to the power level. 43 ******************************************************************************/ 44 static void __init psci_init_pwr_domain_node(uint16_t node_idx, 45 unsigned int parent_idx, 46 unsigned char level) 47 { 48 if (level > PSCI_CPU_PWR_LVL) { 49 assert(node_idx < PSCI_NUM_NON_CPU_PWR_DOMAINS); 50 51 psci_non_cpu_pd_nodes[node_idx].level = level; 52 psci_lock_init(psci_non_cpu_pd_nodes, node_idx); 53 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; 54 psci_non_cpu_pd_nodes[node_idx].local_state = 55 PLAT_MAX_OFF_STATE; 56 } else { 57 psci_cpu_data_t *svc_cpu_data; 58 59 assert(node_idx < PLATFORM_CORE_COUNT); 60 61 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; 62 63 /* Initialize with an invalid mpidr */ 64 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; 65 66 svc_cpu_data = 67 &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data); 68 69 /* Set the Affinity Info for the cores as OFF */ 70 svc_cpu_data->aff_info_state = AFF_STATE_OFF; 71 72 /* Default to the highest power level when the cpu is not suspending */ 73 svc_cpu_data->target_pwrlvl = PLAT_MAX_PWR_LVL; 74 75 /* Set the power state to OFF state */ 76 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; 77 78 psci_flush_dcache_range((uintptr_t)svc_cpu_data, 79 sizeof(*svc_cpu_data)); 80 81 cm_set_context_by_index(node_idx, 82 (void *) &psci_ns_context[node_idx], 83 NON_SECURE); 84 } 85 } 86 87 /******************************************************************************* 88 * This functions updates cpu_start_idx and ncpus field for each of the node in 89 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of 90 * the CPUs and check whether they match with the parent of the previous 91 * CPU. The basic assumption for this work is that children of the same parent 92 * are allocated adjacent indices. The platform should ensure this though proper 93 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and 94 * plat_my_core_pos() APIs. 95 *******************************************************************************/ 96 static void __init psci_update_pwrlvl_limits(void) 97 { 98 unsigned int cpu_idx; 99 int j; 100 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; 101 unsigned int temp_index[PLAT_MAX_PWR_LVL]; 102 103 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 104 psci_get_parent_pwr_domain_nodes(cpu_idx, 105 PLAT_MAX_PWR_LVL, 106 temp_index); 107 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { 108 if (temp_index[j] != nodes_idx[j]) { 109 nodes_idx[j] = temp_index[j]; 110 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx 111 = cpu_idx; 112 } 113 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; 114 } 115 } 116 } 117 118 static void __init populate_cpu_data(void) 119 { 120 for (unsigned int idx = 0; idx < psci_plat_core_count; idx++) { 121 set_cpu_data_by_index(idx, warmboot_ep_info, &warmboot_ep_info[idx]); 122 } 123 } 124 125 /******************************************************************************* 126 * Core routine to populate the power domain tree. The tree descriptor passed by 127 * the platform is populated breadth-first and the first entry in the map 128 * informs the number of root power domains. The parent nodes of the root nodes 129 * will point to an invalid entry(-1). 130 ******************************************************************************/ 131 static unsigned int __init populate_power_domain_tree(const unsigned char 132 *topology) 133 { 134 unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; 135 unsigned int node_index = 0U, num_children; 136 unsigned int parent_node_index = 0U; 137 int level = (int)PLAT_MAX_PWR_LVL; 138 139 /* 140 * For each level the inputs are: 141 * - number of nodes at this level in plat_array i.e. num_nodes_at_level 142 * This is the sum of values of nodes at the parent level. 143 * - Index of first entry at this level in the plat_array i.e. 144 * parent_node_index. 145 * - Index of first free entry in psci_non_cpu_pd_nodes[] or 146 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. 147 */ 148 while (level >= (int) PSCI_CPU_PWR_LVL) { 149 num_nodes_at_next_lvl = 0U; 150 /* 151 * For each entry (parent node) at this level in the plat_array: 152 * - Find the number of children 153 * - Allocate a node in a power domain array for each child 154 * - Set the parent of the child to the parent_node_index - 1 155 * - Increment parent_node_index to point to the next parent 156 * - Accumulate the number of children at next level. 157 */ 158 for (i = 0U; i < num_nodes_at_lvl; i++) { 159 assert(parent_node_index <= 160 PSCI_NUM_NON_CPU_PWR_DOMAINS); 161 num_children = topology[parent_node_index]; 162 163 for (j = node_index; 164 j < (node_index + num_children); j++) 165 psci_init_pwr_domain_node((uint16_t)j, 166 parent_node_index - 1U, 167 (unsigned char)level); 168 169 node_index = j; 170 num_nodes_at_next_lvl += num_children; 171 parent_node_index++; 172 } 173 174 num_nodes_at_lvl = num_nodes_at_next_lvl; 175 level--; 176 177 /* Reset the index for the cpu power domain array */ 178 if (level == (int) PSCI_CPU_PWR_LVL) 179 node_index = 0; 180 } 181 182 /* Validate the sanity of array exported by the platform */ 183 assert(j <= PLATFORM_CORE_COUNT); 184 return j; 185 } 186 187 /******************************************************************************* 188 * This function does the architectural setup and takes the warm boot 189 * entry-point `mailbox_ep` as an argument. The function also initializes the 190 * power domain topology tree by querying the platform. The power domain nodes 191 * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and 192 * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform 193 * exports its static topology map through the 194 * populate_power_domain_topology_tree() API. The algorithm populates the 195 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this 196 * topology map. On a platform that implements two clusters of 2 cpus each, 197 * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would 198 * look like this: 199 * 200 * --------------------------------------------------- 201 * | system node | cluster 0 node | cluster 1 node | 202 * --------------------------------------------------- 203 * 204 * And populated psci_cpu_pd_nodes would look like this : 205 * <- cpus cluster0 -><- cpus cluster1 -> 206 * ------------------------------------------------ 207 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | 208 * ------------------------------------------------ 209 ******************************************************************************/ 210 int __init psci_setup(const psci_lib_args_t *lib_args) 211 { 212 const unsigned char *topology_tree; 213 unsigned int cpu_idx = plat_my_core_pos(); 214 215 assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args)); 216 217 /* Do the Architectural initialization */ 218 psci_arch_setup(); 219 220 /* Query the topology map from the platform */ 221 topology_tree = plat_get_power_domain_tree_desc(); 222 223 /* Populate the power domain arrays using the platform topology map */ 224 psci_plat_core_count = populate_power_domain_tree(topology_tree); 225 226 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ 227 psci_update_pwrlvl_limits(); 228 229 /* Initialise the warmboot entrypoints */ 230 populate_cpu_data(); 231 232 /* Populate the mpidr field of cpu node for this CPU */ 233 psci_cpu_pd_nodes[cpu_idx].mpidr = 234 read_mpidr() & MPIDR_AFFINITY_MASK; 235 236 psci_init_req_local_pwr_states(); 237 238 /* 239 * Set the requested and target state of this CPU and all the higher 240 * power domain levels for this CPU to run. 241 */ 242 psci_set_pwr_domains_to_run(cpu_idx, PLAT_MAX_PWR_LVL); 243 244 (void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, 245 &psci_plat_pm_ops); 246 assert(psci_plat_pm_ops != NULL); 247 248 /* 249 * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs 250 * during warm boot, possibly before data cache is enabled. 251 */ 252 psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops, 253 sizeof(psci_plat_pm_ops)); 254 255 /* Initialize the psci capability */ 256 psci_caps = PSCI_GENERIC_CAP; 257 258 if (psci_plat_pm_ops->pwr_domain_off != NULL) { 259 psci_caps |= define_psci_cap(PSCI_CPU_OFF); 260 } 261 if ((psci_plat_pm_ops->pwr_domain_on != NULL) && 262 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)) { 263 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); 264 } 265 if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) && 266 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) { 267 if (psci_plat_pm_ops->validate_power_state != NULL) { 268 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); 269 } 270 if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL) { 271 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); 272 } 273 #if PSCI_OS_INIT_MODE 274 psci_caps |= define_psci_cap(PSCI_SET_SUSPEND_MODE); 275 #endif 276 } 277 if (psci_plat_pm_ops->system_off != NULL) { 278 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); 279 } 280 if (psci_plat_pm_ops->system_reset != NULL) { 281 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); 282 } 283 if (psci_plat_pm_ops->get_node_hw_state != NULL) { 284 psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64); 285 } 286 if ((psci_plat_pm_ops->read_mem_protect != NULL) && 287 (psci_plat_pm_ops->write_mem_protect != NULL)) { 288 psci_caps |= define_psci_cap(PSCI_MEM_PROTECT); 289 } 290 if (psci_plat_pm_ops->mem_protect_chk != NULL) { 291 psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64); 292 } 293 if (psci_plat_pm_ops->system_reset2 != NULL) { 294 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64); 295 } 296 #if ENABLE_PSCI_STAT 297 psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64); 298 psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64); 299 #endif 300 301 return 0; 302 } 303 304 /******************************************************************************* 305 * This duplicates what the primary cpu did after a cold boot in BL1. The same 306 * needs to be done when a cpu is hotplugged in. This function could also over- 307 * ride any EL3 setup done by BL1 as this code resides in rw memory. 308 ******************************************************************************/ 309 void psci_arch_setup(void) 310 { 311 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) 312 /* Program the counter frequency */ 313 write_cntfrq_el0(plat_get_syscnt_freq2()); 314 #endif 315 316 /* Initialize the cpu_ops pointer. */ 317 init_cpu_ops(); 318 319 /* Having initialized cpu_ops, we can now print errata status */ 320 print_errata_status(); 321 322 } 323 324 /****************************************************************************** 325 * PSCI Library interface to initialize the cpu context for the next non 326 * secure image during cold boot. The relevant registers in the cpu context 327 * need to be retrieved and programmed on return from this interface. 328 *****************************************************************************/ 329 void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info) 330 { 331 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); 332 cm_init_my_context(next_image_info); 333 cm_prepare_el3_exit(NON_SECURE); 334 } 335