1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <stdbool.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 20 /* 21 * The PSCI capability which are provided by the generic code but does not 22 * depend on the platform or spd capabilities. 23 */ 24 #define PSCI_GENERIC_CAP \ 25 (define_psci_cap(PSCI_VERSION) | \ 26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 27 define_psci_cap(PSCI_FEATURES)) 28 29 /* 30 * The PSCI capabilities mask for 64 bit functions. 31 */ 32 #define PSCI_CAP_64BIT_MASK \ 33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 36 define_psci_cap(PSCI_MIG_AARCH64) | \ 37 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 38 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 39 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 41 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 42 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 44 45 /* Internally PSCI uses a uint16_t for various cpu indexes so 46 * define a limit to number of CPUs that can be initialised. 47 */ 48 #define PSCI_MAX_CPUS_INDEX 0xFFFFU 49 50 /* 51 * Helper functions to get/set the fields of PSCI per-cpu data. 52 */ 53 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 54 { 55 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 56 } 57 58 static inline aff_info_state_t psci_get_aff_info_state(void) 59 { 60 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 61 } 62 63 static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx) 64 { 65 return get_cpu_data_by_index(idx, 66 psci_svc_cpu_data.aff_info_state); 67 } 68 69 static inline void psci_set_aff_info_state_by_idx(unsigned int idx, 70 aff_info_state_t aff_state) 71 { 72 set_cpu_data_by_index(idx, 73 psci_svc_cpu_data.aff_info_state, aff_state); 74 } 75 76 static inline unsigned int psci_get_suspend_pwrlvl(void) 77 { 78 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 79 } 80 81 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 82 { 83 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 84 } 85 86 static inline void psci_set_cpu_local_state(plat_local_state_t state) 87 { 88 set_cpu_data(psci_svc_cpu_data.local_state, state); 89 } 90 91 static inline plat_local_state_t psci_get_cpu_local_state(void) 92 { 93 return get_cpu_data(psci_svc_cpu_data.local_state); 94 } 95 96 static inline plat_local_state_t psci_get_cpu_local_state_by_idx( 97 unsigned int idx) 98 { 99 return get_cpu_data_by_index(idx, 100 psci_svc_cpu_data.local_state); 101 } 102 103 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 104 static inline bool is_cpu_standby_req(unsigned int is_power_down_state, 105 unsigned int retn_lvl) 106 { 107 return (is_power_down_state == 0U) && (retn_lvl == 0U); 108 } 109 110 /******************************************************************************* 111 * The following two data structures implement the power domain tree. The tree 112 * is used to track the state of all the nodes i.e. power domain instances 113 * described by the platform. The tree consists of nodes that describe CPU power 114 * domains i.e. leaf nodes and all other power domains which are parents of a 115 * CPU power domain i.e. non-leaf nodes. 116 ******************************************************************************/ 117 typedef struct non_cpu_pwr_domain_node { 118 /* 119 * Index of the first CPU power domain node level 0 which has this node 120 * as its parent. 121 */ 122 unsigned int cpu_start_idx; 123 124 /* 125 * Number of CPU power domains which are siblings of the domain indexed 126 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 127 * -> cpu_start_idx + ncpus' have this node as their parent. 128 */ 129 unsigned int ncpus; 130 131 /* 132 * Index of the parent power domain node. 133 * TODO: Figure out whether to whether using pointer is more efficient. 134 */ 135 unsigned int parent_node; 136 137 plat_local_state_t local_state; 138 139 unsigned char level; 140 141 /* For indexing the psci_lock array*/ 142 uint16_t lock_index; 143 } non_cpu_pd_node_t; 144 145 typedef struct cpu_pwr_domain_node { 146 u_register_t mpidr; 147 148 /* 149 * Index of the parent power domain node. 150 * TODO: Figure out whether to whether using pointer is more efficient. 151 */ 152 unsigned int parent_node; 153 154 /* 155 * A CPU power domain does not require state coordination like its 156 * parent power domains. Hence this node does not include a bakery 157 * lock. A spinlock is required by the CPU_ON handler to prevent a race 158 * when multiple CPUs try to turn ON the same target CPU. 159 */ 160 spinlock_t cpu_lock; 161 } cpu_pd_node_t; 162 163 /******************************************************************************* 164 * The following are helpers and declarations of locks. 165 ******************************************************************************/ 166 #if HW_ASSISTED_COHERENCY 167 /* 168 * On systems where participant CPUs are cache-coherent, we can use spinlocks 169 * instead of bakery locks. 170 */ 171 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 172 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 173 174 /* One lock is required per non-CPU power domain node */ 175 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 176 177 /* 178 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 179 * as PSCI participants are cache-coherent, and there's no need for explicit 180 * cache maintenance operations or barriers to coordinate their state. 181 */ 182 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 183 size_t __unused size) 184 { 185 /* Empty */ 186 } 187 188 #define psci_flush_cpu_data(member) 189 #define psci_inv_cpu_data(member) 190 191 static inline void psci_dsbish(void) 192 { 193 /* Empty */ 194 } 195 196 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 197 { 198 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 199 } 200 201 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 202 { 203 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 204 } 205 206 #else /* if HW_ASSISTED_COHERENCY == 0 */ 207 /* 208 * Use bakery locks for state coordination as not all PSCI participants are 209 * cache coherent. 210 */ 211 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 212 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 213 214 /* One lock is required per non-CPU power domain node */ 215 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 216 217 /* 218 * If not all PSCI participants are cache-coherent, perform cache maintenance 219 * and issue barriers wherever required to coordinate state. 220 */ 221 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 222 { 223 flush_dcache_range(addr, size); 224 } 225 226 #define psci_flush_cpu_data(member) flush_cpu_data(member) 227 #define psci_inv_cpu_data(member) inv_cpu_data(member) 228 229 static inline void psci_dsbish(void) 230 { 231 dsbish(); 232 } 233 234 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 235 { 236 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 237 } 238 239 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 240 { 241 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 242 } 243 244 #endif /* HW_ASSISTED_COHERENCY */ 245 246 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 247 uint16_t idx) 248 { 249 non_cpu_pd_node[idx].lock_index = idx; 250 } 251 252 /******************************************************************************* 253 * Data prototypes 254 ******************************************************************************/ 255 extern const plat_psci_ops_t *psci_plat_pm_ops; 256 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 257 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 258 extern unsigned int psci_caps; 259 extern unsigned int psci_plat_core_count; 260 261 /******************************************************************************* 262 * SPD's power management hooks registered with PSCI 263 ******************************************************************************/ 264 extern const spd_pm_ops_t *psci_spd_pm; 265 266 /******************************************************************************* 267 * Function prototypes 268 ******************************************************************************/ 269 /* Private exported functions from psci_common.c */ 270 int psci_validate_power_state(unsigned int power_state, 271 psci_power_state_t *state_info); 272 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 273 int psci_validate_mpidr(u_register_t mpidr); 274 void psci_init_req_local_pwr_states(void); 275 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 276 psci_power_state_t *target_state); 277 int psci_validate_entry_point(entry_point_info_t *ep, 278 uintptr_t entrypoint, u_register_t context_id); 279 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 280 unsigned int end_lvl, 281 unsigned int *node_index); 282 void psci_do_state_coordination(unsigned int end_pwrlvl, 283 psci_power_state_t *state_info); 284 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 285 const unsigned int *parent_nodes); 286 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 287 const unsigned int *parent_nodes); 288 int psci_validate_suspend_req(const psci_power_state_t *state_info, 289 unsigned int is_power_down_state); 290 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 291 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 292 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 293 void psci_print_power_domain_map(void); 294 unsigned int psci_is_last_on_cpu(void); 295 int psci_spd_migrate_info(u_register_t *mpidr); 296 void psci_do_pwrdown_sequence(unsigned int power_level); 297 298 /* 299 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 300 * available. Otherwise, this needs post-call stack maintenance, which is 301 * handled in assembly. 302 */ 303 void prepare_cpu_pwr_dwn(unsigned int power_level); 304 305 /* Private exported functions from psci_on.c */ 306 int psci_cpu_on_start(u_register_t target_cpu, 307 const entry_point_info_t *ep); 308 309 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); 310 311 /* Private exported functions from psci_off.c */ 312 int psci_do_cpu_off(unsigned int end_pwrlvl); 313 314 /* Private exported functions from psci_suspend.c */ 315 void psci_cpu_suspend_start(const entry_point_info_t *ep, 316 unsigned int end_pwrlvl, 317 psci_power_state_t *state_info, 318 unsigned int is_power_down_state); 319 320 void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); 321 322 /* Private exported functions from psci_helpers.S */ 323 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 324 void psci_do_pwrup_cache_maintenance(void); 325 326 /* Private exported functions from psci_system_off.c */ 327 void __dead2 psci_system_off(void); 328 void __dead2 psci_system_reset(void); 329 u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie); 330 331 /* Private exported functions from psci_stat.c */ 332 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 333 const psci_power_state_t *state_info); 334 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 335 const psci_power_state_t *state_info); 336 u_register_t psci_stat_residency(u_register_t target_cpu, 337 unsigned int power_state); 338 u_register_t psci_stat_count(u_register_t target_cpu, 339 unsigned int power_state); 340 341 /* Private exported functions from psci_mem_protect.c */ 342 u_register_t psci_mem_protect(unsigned int enable); 343 u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length); 344 345 #endif /* PSCI_PRIVATE_H */ 346