1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <stdbool.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 20 /* 21 * The PSCI capability which are provided by the generic code but does not 22 * depend on the platform or spd capabilities. 23 */ 24 #define PSCI_GENERIC_CAP \ 25 (define_psci_cap(PSCI_VERSION) | \ 26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 27 define_psci_cap(PSCI_FEATURES)) 28 29 /* 30 * The PSCI capabilities mask for 64 bit functions. 31 */ 32 #define PSCI_CAP_64BIT_MASK \ 33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 36 define_psci_cap(PSCI_MIG_AARCH64) | \ 37 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 38 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 39 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 41 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 42 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 44 45 /* Internally PSCI uses a uint16_t for various cpu indexes so 46 * define a limit to number of CPUs that can be initialised. 47 */ 48 #define PSCI_MAX_CPUS_INDEX 0xFFFFU 49 50 /* Invalid parent */ 51 #define PSCI_PARENT_NODE_INVALID 0xFFFFFFFFU 52 53 /* 54 * Helper functions to get/set the fields of PSCI per-cpu data. 55 */ 56 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 57 { 58 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 59 } 60 61 static inline aff_info_state_t psci_get_aff_info_state(void) 62 { 63 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 64 } 65 66 static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx) 67 { 68 return get_cpu_data_by_index(idx, 69 psci_svc_cpu_data.aff_info_state); 70 } 71 72 static inline void psci_set_aff_info_state_by_idx(unsigned int idx, 73 aff_info_state_t aff_state) 74 { 75 set_cpu_data_by_index(idx, 76 psci_svc_cpu_data.aff_info_state, aff_state); 77 } 78 79 static inline unsigned int psci_get_suspend_pwrlvl(void) 80 { 81 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 82 } 83 84 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 85 { 86 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 87 } 88 89 static inline void psci_set_cpu_local_state(plat_local_state_t state) 90 { 91 set_cpu_data(psci_svc_cpu_data.local_state, state); 92 } 93 94 static inline plat_local_state_t psci_get_cpu_local_state(void) 95 { 96 return get_cpu_data(psci_svc_cpu_data.local_state); 97 } 98 99 static inline plat_local_state_t psci_get_cpu_local_state_by_idx( 100 unsigned int idx) 101 { 102 return get_cpu_data_by_index(idx, 103 psci_svc_cpu_data.local_state); 104 } 105 106 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 107 static inline bool is_cpu_standby_req(unsigned int is_power_down_state, 108 unsigned int retn_lvl) 109 { 110 return (is_power_down_state == 0U) && (retn_lvl == 0U); 111 } 112 113 /******************************************************************************* 114 * The following two data structures implement the power domain tree. The tree 115 * is used to track the state of all the nodes i.e. power domain instances 116 * described by the platform. The tree consists of nodes that describe CPU power 117 * domains i.e. leaf nodes and all other power domains which are parents of a 118 * CPU power domain i.e. non-leaf nodes. 119 ******************************************************************************/ 120 typedef struct non_cpu_pwr_domain_node { 121 /* 122 * Index of the first CPU power domain node level 0 which has this node 123 * as its parent. 124 */ 125 unsigned int cpu_start_idx; 126 127 /* 128 * Number of CPU power domains which are siblings of the domain indexed 129 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 130 * -> cpu_start_idx + ncpus' have this node as their parent. 131 */ 132 unsigned int ncpus; 133 134 /* 135 * Index of the parent power domain node. 136 * TODO: Figure out whether to whether using pointer is more efficient. 137 */ 138 unsigned int parent_node; 139 140 plat_local_state_t local_state; 141 142 unsigned char level; 143 144 /* For indexing the psci_lock array*/ 145 uint16_t lock_index; 146 } non_cpu_pd_node_t; 147 148 typedef struct cpu_pwr_domain_node { 149 u_register_t mpidr; 150 151 /* 152 * Index of the parent power domain node. 153 * TODO: Figure out whether to whether using pointer is more efficient. 154 */ 155 unsigned int parent_node; 156 157 /* 158 * A CPU power domain does not require state coordination like its 159 * parent power domains. Hence this node does not include a bakery 160 * lock. A spinlock is required by the CPU_ON handler to prevent a race 161 * when multiple CPUs try to turn ON the same target CPU. 162 */ 163 spinlock_t cpu_lock; 164 } cpu_pd_node_t; 165 166 /******************************************************************************* 167 * The following are helpers and declarations of locks. 168 ******************************************************************************/ 169 #if HW_ASSISTED_COHERENCY 170 /* 171 * On systems where participant CPUs are cache-coherent, we can use spinlocks 172 * instead of bakery locks. 173 */ 174 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 175 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 176 177 /* One lock is required per non-CPU power domain node */ 178 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 179 180 /* 181 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 182 * as PSCI participants are cache-coherent, and there's no need for explicit 183 * cache maintenance operations or barriers to coordinate their state. 184 */ 185 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 186 size_t __unused size) 187 { 188 /* Empty */ 189 } 190 191 #define psci_flush_cpu_data(member) 192 #define psci_inv_cpu_data(member) 193 194 static inline void psci_dsbish(void) 195 { 196 /* Empty */ 197 } 198 199 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 200 { 201 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 202 } 203 204 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 205 { 206 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 207 } 208 209 #else /* if HW_ASSISTED_COHERENCY == 0 */ 210 /* 211 * Use bakery locks for state coordination as not all PSCI participants are 212 * cache coherent. 213 */ 214 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 215 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 216 217 /* One lock is required per non-CPU power domain node */ 218 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 219 220 /* 221 * If not all PSCI participants are cache-coherent, perform cache maintenance 222 * and issue barriers wherever required to coordinate state. 223 */ 224 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 225 { 226 flush_dcache_range(addr, size); 227 } 228 229 #define psci_flush_cpu_data(member) flush_cpu_data(member) 230 #define psci_inv_cpu_data(member) inv_cpu_data(member) 231 232 static inline void psci_dsbish(void) 233 { 234 dsbish(); 235 } 236 237 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 238 { 239 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 240 } 241 242 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 243 { 244 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 245 } 246 247 #endif /* HW_ASSISTED_COHERENCY */ 248 249 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 250 uint16_t idx) 251 { 252 non_cpu_pd_node[idx].lock_index = idx; 253 } 254 255 /******************************************************************************* 256 * Data prototypes 257 ******************************************************************************/ 258 extern const plat_psci_ops_t *psci_plat_pm_ops; 259 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 260 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 261 extern unsigned int psci_caps; 262 extern unsigned int psci_plat_core_count; 263 264 /******************************************************************************* 265 * SPD's power management hooks registered with PSCI 266 ******************************************************************************/ 267 extern const spd_pm_ops_t *psci_spd_pm; 268 269 /******************************************************************************* 270 * Function prototypes 271 ******************************************************************************/ 272 /* Private exported functions from psci_common.c */ 273 int psci_validate_power_state(unsigned int power_state, 274 psci_power_state_t *state_info); 275 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 276 int psci_validate_mpidr(u_register_t mpidr); 277 void psci_init_req_local_pwr_states(void); 278 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 279 psci_power_state_t *target_state); 280 int psci_validate_entry_point(entry_point_info_t *ep, 281 uintptr_t entrypoint, u_register_t context_id); 282 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 283 unsigned int end_lvl, 284 unsigned int *node_index); 285 void psci_do_state_coordination(unsigned int end_pwrlvl, 286 psci_power_state_t *state_info); 287 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 288 const unsigned int *parent_nodes); 289 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 290 const unsigned int *parent_nodes); 291 int psci_validate_suspend_req(const psci_power_state_t *state_info, 292 unsigned int is_power_down_state); 293 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 294 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 295 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 296 void psci_print_power_domain_map(void); 297 bool psci_is_last_on_cpu(void); 298 int psci_spd_migrate_info(u_register_t *mpidr); 299 300 /* 301 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 302 * available. Otherwise, this needs post-call stack maintenance, which is 303 * handled in assembly. 304 */ 305 void prepare_cpu_pwr_dwn(unsigned int power_level); 306 307 /* This function applies various CPU errata during power down. */ 308 void apply_cpu_pwr_dwn_errata(void); 309 310 /* Private exported functions from psci_on.c */ 311 int psci_cpu_on_start(u_register_t target_cpu, 312 const entry_point_info_t *ep); 313 314 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); 315 316 /* Private exported functions from psci_off.c */ 317 int psci_do_cpu_off(unsigned int end_pwrlvl); 318 319 /* Private exported functions from psci_suspend.c */ 320 void psci_cpu_suspend_start(const entry_point_info_t *ep, 321 unsigned int end_pwrlvl, 322 psci_power_state_t *state_info, 323 unsigned int is_power_down_state); 324 325 void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); 326 327 /* Private exported functions from psci_helpers.S */ 328 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 329 void psci_do_pwrup_cache_maintenance(void); 330 331 /* Private exported functions from psci_system_off.c */ 332 void __dead2 psci_system_off(void); 333 void __dead2 psci_system_reset(void); 334 u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie); 335 336 /* Private exported functions from psci_stat.c */ 337 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 338 const psci_power_state_t *state_info); 339 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 340 const psci_power_state_t *state_info); 341 u_register_t psci_stat_residency(u_register_t target_cpu, 342 unsigned int power_state); 343 u_register_t psci_stat_count(u_register_t target_cpu, 344 unsigned int power_state); 345 346 /* Private exported functions from psci_mem_protect.c */ 347 u_register_t psci_mem_protect(unsigned int enable); 348 u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length); 349 350 #endif /* PSCI_PRIVATE_H */ 351