1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <stdbool.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 20 /* 21 * The PSCI capability which are provided by the generic code but does not 22 * depend on the platform or spd capabilities. 23 */ 24 #define PSCI_GENERIC_CAP \ 25 (define_psci_cap(PSCI_VERSION) | \ 26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 27 define_psci_cap(PSCI_FEATURES)) 28 29 /* 30 * The PSCI capabilities mask for 64 bit functions. 31 */ 32 #define PSCI_CAP_64BIT_MASK \ 33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 36 define_psci_cap(PSCI_MIG_AARCH64) | \ 37 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 38 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 39 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 41 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 42 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 44 45 /* 46 * Helper functions to get/set the fields of PSCI per-cpu data. 47 */ 48 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 49 { 50 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 51 } 52 53 static inline aff_info_state_t psci_get_aff_info_state(void) 54 { 55 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 56 } 57 58 static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx) 59 { 60 return get_cpu_data_by_index((unsigned int)idx, 61 psci_svc_cpu_data.aff_info_state); 62 } 63 64 static inline void psci_set_aff_info_state_by_idx(int idx, 65 aff_info_state_t aff_state) 66 { 67 set_cpu_data_by_index((unsigned int)idx, 68 psci_svc_cpu_data.aff_info_state, aff_state); 69 } 70 71 static inline unsigned int psci_get_suspend_pwrlvl(void) 72 { 73 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 74 } 75 76 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 77 { 78 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 79 } 80 81 static inline void psci_set_cpu_local_state(plat_local_state_t state) 82 { 83 set_cpu_data(psci_svc_cpu_data.local_state, state); 84 } 85 86 static inline plat_local_state_t psci_get_cpu_local_state(void) 87 { 88 return get_cpu_data(psci_svc_cpu_data.local_state); 89 } 90 91 static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx) 92 { 93 return get_cpu_data_by_index((unsigned int)idx, 94 psci_svc_cpu_data.local_state); 95 } 96 97 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 98 static inline bool is_cpu_standby_req(unsigned int is_power_down_state, 99 unsigned int retn_lvl) 100 { 101 return (is_power_down_state == 0U) && (retn_lvl == 0U); 102 } 103 104 /******************************************************************************* 105 * The following two data structures implement the power domain tree. The tree 106 * is used to track the state of all the nodes i.e. power domain instances 107 * described by the platform. The tree consists of nodes that describe CPU power 108 * domains i.e. leaf nodes and all other power domains which are parents of a 109 * CPU power domain i.e. non-leaf nodes. 110 ******************************************************************************/ 111 typedef struct non_cpu_pwr_domain_node { 112 /* 113 * Index of the first CPU power domain node level 0 which has this node 114 * as its parent. 115 */ 116 int cpu_start_idx; 117 118 /* 119 * Number of CPU power domains which are siblings of the domain indexed 120 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 121 * -> cpu_start_idx + ncpus' have this node as their parent. 122 */ 123 unsigned int ncpus; 124 125 /* 126 * Index of the parent power domain node. 127 * TODO: Figure out whether to whether using pointer is more efficient. 128 */ 129 unsigned int parent_node; 130 131 plat_local_state_t local_state; 132 133 unsigned char level; 134 135 /* For indexing the psci_lock array*/ 136 unsigned char lock_index; 137 } non_cpu_pd_node_t; 138 139 typedef struct cpu_pwr_domain_node { 140 u_register_t mpidr; 141 142 /* 143 * Index of the parent power domain node. 144 * TODO: Figure out whether to whether using pointer is more efficient. 145 */ 146 unsigned int parent_node; 147 148 /* 149 * A CPU power domain does not require state coordination like its 150 * parent power domains. Hence this node does not include a bakery 151 * lock. A spinlock is required by the CPU_ON handler to prevent a race 152 * when multiple CPUs try to turn ON the same target CPU. 153 */ 154 spinlock_t cpu_lock; 155 } cpu_pd_node_t; 156 157 /******************************************************************************* 158 * The following are helpers and declarations of locks. 159 ******************************************************************************/ 160 #if HW_ASSISTED_COHERENCY 161 /* 162 * On systems where participant CPUs are cache-coherent, we can use spinlocks 163 * instead of bakery locks. 164 */ 165 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 166 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 167 168 /* One lock is required per non-CPU power domain node */ 169 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 170 171 /* 172 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 173 * as PSCI participants are cache-coherent, and there's no need for explicit 174 * cache maintenance operations or barriers to coordinate their state. 175 */ 176 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 177 size_t __unused size) 178 { 179 /* Empty */ 180 } 181 182 #define psci_flush_cpu_data(member) 183 #define psci_inv_cpu_data(member) 184 185 static inline void psci_dsbish(void) 186 { 187 /* Empty */ 188 } 189 190 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 191 { 192 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 193 } 194 195 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 196 { 197 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 198 } 199 200 #else /* if HW_ASSISTED_COHERENCY == 0 */ 201 /* 202 * Use bakery locks for state coordination as not all PSCI participants are 203 * cache coherent. 204 */ 205 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 206 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 207 208 /* One lock is required per non-CPU power domain node */ 209 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 210 211 /* 212 * If not all PSCI participants are cache-coherent, perform cache maintenance 213 * and issue barriers wherever required to coordinate state. 214 */ 215 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 216 { 217 flush_dcache_range(addr, size); 218 } 219 220 #define psci_flush_cpu_data(member) flush_cpu_data(member) 221 #define psci_inv_cpu_data(member) inv_cpu_data(member) 222 223 static inline void psci_dsbish(void) 224 { 225 dsbish(); 226 } 227 228 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 229 { 230 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 231 } 232 233 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 234 { 235 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 236 } 237 238 #endif /* HW_ASSISTED_COHERENCY */ 239 240 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 241 unsigned char idx) 242 { 243 non_cpu_pd_node[idx].lock_index = idx; 244 } 245 246 /******************************************************************************* 247 * Data prototypes 248 ******************************************************************************/ 249 extern const plat_psci_ops_t *psci_plat_pm_ops; 250 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 251 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 252 extern unsigned int psci_caps; 253 254 /******************************************************************************* 255 * SPD's power management hooks registered with PSCI 256 ******************************************************************************/ 257 extern const spd_pm_ops_t *psci_spd_pm; 258 259 /******************************************************************************* 260 * Function prototypes 261 ******************************************************************************/ 262 /* Private exported functions from psci_common.c */ 263 int psci_validate_power_state(unsigned int power_state, 264 psci_power_state_t *state_info); 265 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 266 int psci_validate_mpidr(u_register_t mpidr); 267 void psci_init_req_local_pwr_states(void); 268 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 269 psci_power_state_t *target_state); 270 int psci_validate_entry_point(entry_point_info_t *ep, 271 uintptr_t entrypoint, u_register_t context_id); 272 void psci_get_parent_pwr_domain_nodes(int cpu_idx, 273 unsigned int end_lvl, 274 unsigned int *node_index); 275 void psci_do_state_coordination(unsigned int end_pwrlvl, 276 psci_power_state_t *state_info); 277 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx); 278 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx); 279 int psci_validate_suspend_req(const psci_power_state_t *state_info, 280 unsigned int is_power_down_state); 281 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 282 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 283 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 284 void psci_print_power_domain_map(void); 285 unsigned int psci_is_last_on_cpu(void); 286 int psci_spd_migrate_info(u_register_t *mpidr); 287 void psci_do_pwrdown_sequence(unsigned int power_level); 288 289 /* 290 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 291 * available. Otherwise, this needs post-call stack maintenance, which is 292 * handled in assembly. 293 */ 294 void prepare_cpu_pwr_dwn(unsigned int power_level); 295 296 /* Private exported functions from psci_on.c */ 297 int psci_cpu_on_start(u_register_t target_cpu, 298 const entry_point_info_t *ep); 299 300 void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info); 301 302 /* Private exported functions from psci_off.c */ 303 int psci_do_cpu_off(unsigned int end_pwrlvl); 304 305 /* Private exported functions from psci_suspend.c */ 306 void psci_cpu_suspend_start(const entry_point_info_t *ep, 307 unsigned int end_pwrlvl, 308 psci_power_state_t *state_info, 309 unsigned int is_power_down_state); 310 311 void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info); 312 313 /* Private exported functions from psci_helpers.S */ 314 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 315 void psci_do_pwrup_cache_maintenance(void); 316 317 /* Private exported functions from psci_system_off.c */ 318 void __dead2 psci_system_off(void); 319 void __dead2 psci_system_reset(void); 320 u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie); 321 322 /* Private exported functions from psci_stat.c */ 323 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 324 const psci_power_state_t *state_info); 325 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 326 const psci_power_state_t *state_info); 327 u_register_t psci_stat_residency(u_register_t target_cpu, 328 unsigned int power_state); 329 u_register_t psci_stat_count(u_register_t target_cpu, 330 unsigned int power_state); 331 332 /* Private exported functions from psci_mem_protect.c */ 333 u_register_t psci_mem_protect(unsigned int enable); 334 u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length); 335 336 #endif /* PSCI_PRIVATE_H */ 337