1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <stdbool.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 20 /* 21 * The PSCI capability which are provided by the generic code but does not 22 * depend on the platform or spd capabilities. 23 */ 24 #define PSCI_GENERIC_CAP \ 25 (define_psci_cap(PSCI_VERSION) | \ 26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 27 define_psci_cap(PSCI_FEATURES)) 28 29 /* 30 * The PSCI capabilities mask for 64 bit functions. 31 */ 32 #define PSCI_CAP_64BIT_MASK \ 33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 36 define_psci_cap(PSCI_MIG_AARCH64) | \ 37 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 38 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 39 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 41 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 42 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 44 45 /* 46 * Helper functions to get/set the fields of PSCI per-cpu data. 47 */ 48 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 49 { 50 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 51 } 52 53 static inline aff_info_state_t psci_get_aff_info_state(void) 54 { 55 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 56 } 57 58 static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx) 59 { 60 return get_cpu_data_by_index(idx, 61 psci_svc_cpu_data.aff_info_state); 62 } 63 64 static inline void psci_set_aff_info_state_by_idx(unsigned int idx, 65 aff_info_state_t aff_state) 66 { 67 set_cpu_data_by_index(idx, 68 psci_svc_cpu_data.aff_info_state, aff_state); 69 } 70 71 static inline unsigned int psci_get_suspend_pwrlvl(void) 72 { 73 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 74 } 75 76 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 77 { 78 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 79 } 80 81 static inline void psci_set_cpu_local_state(plat_local_state_t state) 82 { 83 set_cpu_data(psci_svc_cpu_data.local_state, state); 84 } 85 86 static inline plat_local_state_t psci_get_cpu_local_state(void) 87 { 88 return get_cpu_data(psci_svc_cpu_data.local_state); 89 } 90 91 static inline plat_local_state_t psci_get_cpu_local_state_by_idx( 92 unsigned int idx) 93 { 94 return get_cpu_data_by_index(idx, 95 psci_svc_cpu_data.local_state); 96 } 97 98 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 99 static inline bool is_cpu_standby_req(unsigned int is_power_down_state, 100 unsigned int retn_lvl) 101 { 102 return (is_power_down_state == 0U) && (retn_lvl == 0U); 103 } 104 105 /******************************************************************************* 106 * The following two data structures implement the power domain tree. The tree 107 * is used to track the state of all the nodes i.e. power domain instances 108 * described by the platform. The tree consists of nodes that describe CPU power 109 * domains i.e. leaf nodes and all other power domains which are parents of a 110 * CPU power domain i.e. non-leaf nodes. 111 ******************************************************************************/ 112 typedef struct non_cpu_pwr_domain_node { 113 /* 114 * Index of the first CPU power domain node level 0 which has this node 115 * as its parent. 116 */ 117 unsigned int cpu_start_idx; 118 119 /* 120 * Number of CPU power domains which are siblings of the domain indexed 121 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 122 * -> cpu_start_idx + ncpus' have this node as their parent. 123 */ 124 unsigned int ncpus; 125 126 /* 127 * Index of the parent power domain node. 128 * TODO: Figure out whether to whether using pointer is more efficient. 129 */ 130 unsigned int parent_node; 131 132 plat_local_state_t local_state; 133 134 unsigned char level; 135 136 /* For indexing the psci_lock array*/ 137 unsigned char lock_index; 138 } non_cpu_pd_node_t; 139 140 typedef struct cpu_pwr_domain_node { 141 u_register_t mpidr; 142 143 /* 144 * Index of the parent power domain node. 145 * TODO: Figure out whether to whether using pointer is more efficient. 146 */ 147 unsigned int parent_node; 148 149 /* 150 * A CPU power domain does not require state coordination like its 151 * parent power domains. Hence this node does not include a bakery 152 * lock. A spinlock is required by the CPU_ON handler to prevent a race 153 * when multiple CPUs try to turn ON the same target CPU. 154 */ 155 spinlock_t cpu_lock; 156 } cpu_pd_node_t; 157 158 /******************************************************************************* 159 * The following are helpers and declarations of locks. 160 ******************************************************************************/ 161 #if HW_ASSISTED_COHERENCY 162 /* 163 * On systems where participant CPUs are cache-coherent, we can use spinlocks 164 * instead of bakery locks. 165 */ 166 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 167 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 168 169 /* One lock is required per non-CPU power domain node */ 170 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 171 172 /* 173 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 174 * as PSCI participants are cache-coherent, and there's no need for explicit 175 * cache maintenance operations or barriers to coordinate their state. 176 */ 177 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 178 size_t __unused size) 179 { 180 /* Empty */ 181 } 182 183 #define psci_flush_cpu_data(member) 184 #define psci_inv_cpu_data(member) 185 186 static inline void psci_dsbish(void) 187 { 188 /* Empty */ 189 } 190 191 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 192 { 193 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 194 } 195 196 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 197 { 198 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 199 } 200 201 #else /* if HW_ASSISTED_COHERENCY == 0 */ 202 /* 203 * Use bakery locks for state coordination as not all PSCI participants are 204 * cache coherent. 205 */ 206 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 207 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 208 209 /* One lock is required per non-CPU power domain node */ 210 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 211 212 /* 213 * If not all PSCI participants are cache-coherent, perform cache maintenance 214 * and issue barriers wherever required to coordinate state. 215 */ 216 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 217 { 218 flush_dcache_range(addr, size); 219 } 220 221 #define psci_flush_cpu_data(member) flush_cpu_data(member) 222 #define psci_inv_cpu_data(member) inv_cpu_data(member) 223 224 static inline void psci_dsbish(void) 225 { 226 dsbish(); 227 } 228 229 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 230 { 231 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 232 } 233 234 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 235 { 236 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 237 } 238 239 #endif /* HW_ASSISTED_COHERENCY */ 240 241 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 242 unsigned char idx) 243 { 244 non_cpu_pd_node[idx].lock_index = idx; 245 } 246 247 /******************************************************************************* 248 * Data prototypes 249 ******************************************************************************/ 250 extern const plat_psci_ops_t *psci_plat_pm_ops; 251 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 252 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 253 extern unsigned int psci_caps; 254 255 /******************************************************************************* 256 * SPD's power management hooks registered with PSCI 257 ******************************************************************************/ 258 extern const spd_pm_ops_t *psci_spd_pm; 259 260 /******************************************************************************* 261 * Function prototypes 262 ******************************************************************************/ 263 /* Private exported functions from psci_common.c */ 264 int psci_validate_power_state(unsigned int power_state, 265 psci_power_state_t *state_info); 266 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 267 int psci_validate_mpidr(u_register_t mpidr); 268 void psci_init_req_local_pwr_states(void); 269 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 270 psci_power_state_t *target_state); 271 int psci_validate_entry_point(entry_point_info_t *ep, 272 uintptr_t entrypoint, u_register_t context_id); 273 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 274 unsigned int end_lvl, 275 unsigned int *node_index); 276 void psci_do_state_coordination(unsigned int end_pwrlvl, 277 psci_power_state_t *state_info); 278 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 279 const unsigned int *parent_nodes); 280 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 281 const unsigned int *parent_nodes); 282 int psci_validate_suspend_req(const psci_power_state_t *state_info, 283 unsigned int is_power_down_state); 284 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 285 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 286 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 287 void psci_print_power_domain_map(void); 288 unsigned int psci_is_last_on_cpu(void); 289 int psci_spd_migrate_info(u_register_t *mpidr); 290 void psci_do_pwrdown_sequence(unsigned int power_level); 291 292 /* 293 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 294 * available. Otherwise, this needs post-call stack maintenance, which is 295 * handled in assembly. 296 */ 297 void prepare_cpu_pwr_dwn(unsigned int power_level); 298 299 /* Private exported functions from psci_on.c */ 300 int psci_cpu_on_start(u_register_t target_cpu, 301 const entry_point_info_t *ep); 302 303 void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info); 304 305 /* Private exported functions from psci_off.c */ 306 int psci_do_cpu_off(unsigned int end_pwrlvl); 307 308 /* Private exported functions from psci_suspend.c */ 309 void psci_cpu_suspend_start(const entry_point_info_t *ep, 310 unsigned int end_pwrlvl, 311 psci_power_state_t *state_info, 312 unsigned int is_power_down_state); 313 314 void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info); 315 316 /* Private exported functions from psci_helpers.S */ 317 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 318 void psci_do_pwrup_cache_maintenance(void); 319 320 /* Private exported functions from psci_system_off.c */ 321 void __dead2 psci_system_off(void); 322 void __dead2 psci_system_reset(void); 323 u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie); 324 325 /* Private exported functions from psci_stat.c */ 326 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 327 const psci_power_state_t *state_info); 328 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 329 const psci_power_state_t *state_info); 330 u_register_t psci_stat_residency(u_register_t target_cpu, 331 unsigned int power_state); 332 u_register_t psci_stat_count(u_register_t target_cpu, 333 unsigned int power_state); 334 335 /* Private exported functions from psci_mem_protect.c */ 336 u_register_t psci_mem_protect(unsigned int enable); 337 u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length); 338 339 #endif /* PSCI_PRIVATE_H */ 340